Memory device capacitor contact structure and method for preparing same

Patent metadata

Field	Value
Publication number	US-12185519-B2
Application number	US-202117445964-A
Country	US
Kind code	B2
Filing date	Aug 26, 2021
Priority date	Mar 24, 2021
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

A method for preparing a capacitor contact structure of a memory device includes providing a substrate, forming a plurality of bit line structures arranged in parallel and at intervals on the substrate, and the bit line structures extending along a first direction; forming conducting layer structures between adjacent bit line structures, upper surfaces of which are lower than upper surfaces of the bit line structures; forming sacrificial layers on the conducting layer structures; forming a plurality of isolation trenches arranged in parallel and at intervals in the sacrificial layer, the isolation trenches extend along a second direction, and the second direction intersects the first direction; forming isolation dielectric layers in the isolation trenches; and removing the sacrificial layer based on the bit line structure and the isolation dielectric layer to form grooves between adjacent bit line structures and between adjacent isolation dielectric layers, the grooves expose the conducting layer structures.

First claim

What is claimed is:

1. A method for preparing a capacitor contact structure of a memory device, comprising:
providing a substrate, wherein a plurality of bit line structures arranged in parallel and at intervals are formed on the substrate, and the plurality of bit line structures extend along a first direction;
forming a conducting layer structure between two adjacent ones of the plurality of bit line structures, wherein an upper surface of the conducting layer structure is lower than upper surfaces of the two adjacent ones of the plurality of bit line structures;
forming a sacrificial layer on the conducting layer structure;
forming a plurality of isolation trenches arranged in parallel and at intervals in the sacrificial layer and the conducting layer structure, wherein the plurality of isolation trenches extend along a second direction and pass through all the plurality of bit line structures, and the second direction intersects the first direction;
forming isolation dielectric layers, each of the isolation dielectric layers is in each of the plurality of isolation trenches, wherein said forming the isolation dielectric layers comprises forming a first silicon nitride layer on sidewalls and bottom of each of the plurality of isolation trenches;
forming a first silicon oxide layer on a surface of the first silicon nitride layer; and forming a second silicon nitride layer on a surface of the first silicon oxide layer; and
removing the sacrificial layer based on the two adjacent ones of the plurality of bit line structures and the isolation dielectric layers to form grooves each between the two adjacent ones of the plurality of bit line structures and between two adjacent ones of the isolation dielectric layers, wherein the grooves expose the conducting layer structures.

2. The method of claim 1 , wherein
each of the plurality of bit line structures comprises a stacked structure and sidewall structures, the stacked structure comprises a main conducting layer and a top dielectric layer that are stacked, and the sidewall structures are located on sidewalls of the stacked structure; and
a depth of the plurality of isolation trenches located directly above the plurality of bit line structures is less than a height of the top dielectric layer, a depth of each of the plurality of isolation trenches between the two adjacent ones of the plurality of bit line structures is equal to a sum of a thickness of the sacrificial layer and a thickness of the conducting layer structure.

3. The method of claim 2 , wherein
each of the sidewall structures is a stacked sidewall structure including an inner silicon nitride layer, a middle silicon oxide layer and an outer silicon nitride layer that are sequentially stacked from inside to outside; and
after the sacrificial layers are removed, the method further comprises: removing the outer silicon nitride layer and the middle silicon oxide layer of the sidewall structures located above the conducting layer structure.

4. A capacitor contact structure of a memory device prepared with the method of claim 2 .

5. The method of claim 1 , wherein
the conducting layer structure comprises a polysilicon structure, and the sacrificial layer comprises a Spin-on Dielectric (SOD) layer.

6. The method of claim 5 , wherein
the sacrificial layer is removed by a wet etch process.

7. The method of claim 6 , wherein
an etching solution of the wet etch process comprises hydrofluoric acid and deionized water, and a molar ratio of the hydrofluoric acid to the deionized water in the etching solution is 10:1-300:1.

8. A capacitor contact structure of a memory device prepared with the method of claim 5 .

9. The method of claim 1 , wherein said forming the second silicon nitride layer on the surface of the first silicon oxide layer comprises:
forming the second silicon nitride layer filling up each of the plurality of isolation trenches and covering an upper surface of the sacrificial layer and the upper surfaces of the two adjacent ones of the plurality of bit line structures, and prior to removing the sacrificial layer;
removing the second silicon nitride layer on the upper surface of the sacrificial layer and the upper surfaces of the two adjacent ones of the plurality of bit line structures by a dry etching process or a wet etching process.

10. A capacitor contact structure of a memory device prepared with the method of claim 9 .

11. The method of claim 1 , wherein said forming the isolation dielectric layers trenches comprises:
forming a second silicon oxide layer on the sidewalls and the bottoms of each of the isolation trenches; and
forming a third silicon nitride layer on the surface of the second silicon oxide layer.

12. The method of claim 1 , wherein the first direction is orthogonal to the second direction.

13. The method of claim 1 , wherein shallow trench isolation structures are formed in the substrate, and the shallow trench isolation structures isolate a plurality of active regions arranged at intervals in the substrate.

14. The method of claim 13 , wherein
an insulating layer is formed on upper surfaces of the active regions;
before forming the conducting layer structure between the two adjacent ones of the plurality of bit line structures, the method further comprises removing the insulating layer on the upper surfaces of the active regions between the two adjacent ones of the plurality of bit line structures to expose the active regions; and
the conducting layer structure is in contact with the active regions.

15. The method of claim 1 , wherein a plurality of embedded gate word lines arranged in parallel and at intervals are formed in the substrate, and the plurality of embedded gate word lines extend along the second direction.

16. A capacitor contact structure of a memory device prepared with the method of claim 1 .

Assignees

• Changxin Memory Tech Inc

Inventors

• Liu Zhongming
• Bai Shijie
• Chen Longyang

Classifications

• H10B12/485

  Bit line contacts · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title

• H10B12/053

  the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383) · CPC title

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B51/00

  Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors · CPC title