Wide-range inductor-based delay-cell and area efficient termination switch control

Patent metadata

Field	Value
Publication number	US-12184751-B2
Application number	US-202117341150-A
Country	US
Kind code	B2
Filing date	Jun 7, 2021
Priority date	Dec 18, 2020
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

A quadrature clock generator that takes advantage of the inherently low delay of a shunt-series inductively peaked clock buffer to generate quadrature clocks with the high jitter performance using just one additional stage in Q path compared to I path. The generator includes a delay cell that uses shunt-series peaking and uses a resistive DAC in series with the shunt inductor to provide a large delay range with good jitter characteristics. The resistive DAC can be placed near a real or a virtual ground to minimize capacitive loading on the signal path. This delay cell can provide greater than 2× delay tuning range and is suitable for clocks at high frequencies. This delay cell can also be used as a ring oscillator with large frequency tuning range. A low voltage differential signaling termination switch control that uses feed forward mechanism to control termination impedance of device in a receiver.

First claim

What is claimed is:

1. A quadrature generator apparatus comprising:
a first driver to receive a first input and having a first output;
a second driver to receive a second input and having a second output, wherein the first input is complementary of the second input;
a first shunt-series set of inductors coupled to the first output; and
a second shunt-series set of inductors coupled to the second output, wherein the first shunt-series set of inductors is coupled to the second shunt-series set of inductors via a resistor based digital-to-analog converter (R-DAC).

2. The apparatus of claim 1 , comprising a memory element coupled to the first output and the second output.

3. The apparatus of claim 2 , wherein the memory element comprises cross-coupled inverters.

4. The apparatus of claim 3 , wherein the cross-coupled inverters are about eight times smaller than the first driver or the second driver.

5. The apparatus of claim 1 , wherein the R-DAC is operable to adjust jitter and delay of the apparatus.

6. The apparatus of claim 1 , wherein the R-DAC is controlled by a digital code that results in a smallest resistance of the R-DAC causes the apparatus to provide shortest propagation delay and lowest jitter.

7. The apparatus of claim 1 , wherein the R-DAC is controlled by a digital code that results in a highest resistance of the R-DAC causes the apparatus to provide longest propagation delay and highest jitter.

8. The apparatus of claim 1 , wherein the first driver comprises a first inverter, and wherein the second driver comprises a second inverter.

9. The apparatus of claim 1 , wherein the first and second drivers are power gated.

10. The apparatus of claim 1 , wherein the first shunt-series set of inductors includes:
a first inductor coupled in series between the first output and a third output; and
a second inductor coupled with the first output and a node that provides a common mode voltage.

11. The apparatus of claim 10 , wherein the second shunt-series set of inductors comprises:
a third inductor coupled in series between the second output and a fourth output; and
a fourth inductor coupled with the second output and the node.

12. A quadrature generator apparatus comprising:
a I-path to generate an I-clock;
a Q-path to generate Q-clock, wherein the Q-clock is substantially 90 phase-shifted relative to the I-clock; and
a node coupled to the I-path and the Q-path, wherein the node is to receive an input clock;
wherein the I-path comprises:
an inverter;
a first switch capacitor with adjustable capacitance, the first switch coupled to an output of the inverter;
a resistor based digital-to-analog converter (R-DAC);
a second switch capacitor with adjustable capacitance; and
a shunt-series set of inductors comprising a shunt inductor coupled to the R-DAC, and a series inductor coupled to the first switch capacitor and the second switch capacitor.

13. The apparatus of claim 12 , wherein the node is coupled to an input of the inverter of the I-path.

14. The apparatus of claim 12 , wherein the Q-path comprises:
a first inverter;
a first switch capacitor with adjustable capacitance, the first switch coupled to an output of the first inverter;
a second inverter;
a second switch capacitor coupled to an output of the second inverter;
a R-DAC;
a third switch capacitor with adjustable capacitance; and
a shunt-series set of inductors comprising a shunt inductor coupled to the R-DAC, and a series inductor coupled to the second switch capacitor and the third switch capacitor.

15. A computing system with a quadrature generator, comprising:
a processor;
a wireless interface to allow the processor to communicate with another device; and
a memory coupled to the processor, wherein the processor includes a serial-deserializer transmitter which includes a clock buffer which comprises:
a first driver to receive a first input and having a first output;
a second driver to receive a second input and having a second output, wherein the first input is complementary of the second input;
a first shunt-series set of inductors coupled to the first output; and
a second shunt-series set of inductors coupled to the second output, wherein the first shunt-series set of inductors is coupled to the second shunt-series set of inductors via a resistor based digital-to-analog converter (R-DAC).

16. The system of claim 15 , wherein the clock buffer includes a memory element coupled to the first output and the second output.

17. The system of claim 16 , wherein the memory element comprises cross-coupled inverters.

18. The system of claim 17 , wherein the cross-coupled inverters are about eight times smaller than the first driver or the second driver.

19. The system of claim 15 , wherein the R-DAC is operable to adjust jitter and delay of the clock buffer.

20. The system of claim 15 , wherein the R-DAC is controlled by a digital code that results in a smallest resistance of the R-DAC causes the clock buffer to provide shortest propagation delay and lowest jitter.

21. The system of claim 15 , wherein the R-DAC is controlled by a digital code that results in a highest resistance of the R-DAC causes the clock buffer to provide longest propagation delay and highest jitter.

Assignees

• Intel Corp

Inventors

• KUNDU Sandipan
• Balankutty Ajay
• Kim Bong Chan
• Liu Yutao
• Kim Jihwan
• Yu Kai
• Singh Gurmukh
• Kim Stephen
• Packard Richard
• O'Mahony Frank

Classifications

• H03K5/135 Primary

  by the use of time reference signals, e.g. clock signals · CPC title

• H04L7/0025

  interpolation of clock signal · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title

• H03L7/22

  using more than one loop · CPC title

• H03K2005/00032

  DC control of switching transistors · CPC title