Low-noise sampled voltage regulator

Patent metadata

Field	Value
Publication number	US-9501073-B2
Application number	US-201514594290-A
Country	US
Kind code	B2
Filing date	Jan 12, 2015
Priority date	Jan 12, 2015
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A method and voltage regulator comprises a generator that generates an error difference between a reference and regulated voltage. A clocked ADC samples the voltage as a digital stream. A DAC converts the stream to analog signal(s). A current source driven by the signal(s) generate(s) the regulated voltage. The generator may be an op-amp or comparator comprising a buffer and/or a latch. The N-bit ADC may be a Σ-Δ modulator or N 1-bit ADC latches. The N-bit DAC may comprise 1-bit DACs comprising a switched-capacitor summer and a one stage RC LPF. Sampling the error up-converts flicker noise to the clock frequency which the DAC filters out. The current source may comprise N transistors with gates driven by a signal and sources tied to an independent power supply. Each signal may be weighted by a DAC weight. The apparatus may comprise a decoupling capacitor between the regulated voltage and ground.

First claim

What is claimed is:

1. A voltage regulator circuit configured to provide a regulated voltage for a load, that approaches a known reference voltage, comprising:
a voltage error generator configured to generate an error voltage representing a difference between the reference voltage and the regulated voltage;
a first clock signal at a first clock frequency;
converter configured to sample the error voltage at the first clock frequency and generate a first control signal in which a noise component of the error voltage is up-converted to substantially the first clock frequency;
a filter configured to generate at least one second control signal from the first control signal in which the up-converted noise thereof is substantially reduced from the at least one second control signal; and
a voltage-controlled current source driven by the at least one second control signal configured to generate the regulated voltage supply.

2. A voltage regulator circuit according to claim 1 , wherein the voltage error generator has a first input coupled to the reference voltage and a second input coupled to the regulated voltage supply generated by the voltage-controlled current source.

3. A voltage regulator circuit according to claim 1 , wherein the voltage error generator is a comparator.

4. A voltage regulator circuit according to claim 3 , wherein the comparator comprises a voltage buffer.

5. A voltage regulator circuit according to claim 3 , wherein the comparator comprises at least one sampling latch.

6. A voltage regulator circuit according to claim 3 , wherein the comparator is clocked by a second clock signal and the error voltage is a sampled error signal sampled at a frequency of the second clock signal.

7. A voltage regulator circuit according to claim 6 , wherein the first and second clock signals have a common frequency.

8. A voltage regulator circuit according to claim 7 , wherein the first and second clock signals are the same.

9. A voltage regulator circuit according to claim 1 , wherein the error voltage is a continuous time error signal.

10. A voltage regulator circuit according to claim 1 , wherein the voltage error generator is an operational amplifier (Op-Amp).

11. A voltage regulator circuit according to claim 1 , wherein the voltage error generator is supplied by a power supply that is independent of a power supply for the voltage controlled current source.

12. A voltage regulator circuit according to claim 1 , wherein the voltage error generator has differential outputs for generating a differential error voltage signal.

13. A voltage regulator circuit according to claim 1 , wherein the first clock frequency is in excess of 100 Hz.

14. A voltage regulator circuit according to claim 13 , wherein the first clock frequency is about 9.6 GHz.

15. A voltage regulator circuit according to claim 13 , wherein the first clock frequency is about 19.6 GHz.

16. A voltage regulator circuit according to claim 1 , wherein the first clock signal is generated by the load.

17. A voltage regulator circuit according to claim 1 , wherein the converter is an N-bit analog-to-digital converter (ADC) that generates an N-bit digital control stream as the first control signal.

18. A voltage regulator circuit according to claim 17 , wherein N is 1.

19. A voltage regulator circuit according to claim 17 , where N exceeds 1 and the ADC comprises a plurality of sampling latches each comprising a 1-bit ADC, each configured to generate one bit of the N-bit digital control stream.

20. A voltage regular circuit according to claim 1 , wherein the converter is a Sigma-Delta (Σ-Δ) modulator.

21. A voltage regulator circuit according to claim 1 , wherein the converter is supplied by a power supply that is independent of a power supply for the voltage-controlled current source.

22. A voltage regulator circuit according to claim 1 , wherein the converter has differential inputs for accepting a differential error voltage signal.

23. A voltage regulator circuit according to claim 1 , wherein the filter is an N-bit digital-to-analog (DAC) for converting the first control signal that is an N-bit digital control stream.

24. A voltage regulator according to claim 23 , wherein N is 1.

25. A voltage regulator circuit according to claim 23 , where N exceeds 1 and the DAC comprises a plurality of 1-bit DACs, each configured to convert one bit of the N-bit digital control stream.

26. A voltage regulator circuit according to claim 1 , wherein the filter comprises a switched-capacitor charge summer.

27. A voltage regulator circuit according to claim 1 , wherein the filter comprises a low pass filter.

28. A voltage regulator circuit according to claim 27 , wherein the low pass filter is a one-stage RC filter.

29. A voltage regulator circuit according to claim 1 , wherein the filter is clocked by a second clock signal and the error voltage is a sampled-error signal sampled at a frequency of the second clock signal.

30. A voltage regulator circuit according to claim 29 , wherein the first and second clock signals have a common frequency.

31. A voltage regulator circuit according to claim 30 , wherein the first and second clock signals are the same.

32. A voltage regulator circuit according to claim 1 , wherein the filter is supplied by a power supply that is independent of a power supply for the voltage-controlled current source.

33. A voltage regulator circuit according to claim 1 , wherein the voltage-controlled current source comprises at least one transistor.

34. A voltage regulator circuit according to claim 33 , wherein the at least one transistor has a gate driven by one of the at least one second control signals.

35. A voltage regulator circuit according to claim 34 , wherein the at least one second control signal is weighted to correspond to a weight of the filter from which the at least one second control signal emanates.

36. A voltage regulator circuit according to claim 33 , wherein the at least one transistor has a source coupled to a power supply that is independent of any power supply that may provide power for a component selected from a group consisting of the feedback element, the converter, the filter and any combination of any of these.

37. A voltage regulator circuit according to claim 33 , wherein the at least one transistor has a drain coupled to the regulated voltage supply and to an input of the voltage error generator.

38. A voltage regulator circuit according to claim 1 , further comprising a decoupling capacitor positioned between the regulated voltage supply and ground.

39. A voltage regulator circuit according to claim 1 , wherein the voltage regulator circuit comprises an integrated circuit.

40. A voltage regulator circuit according to claim 1 , wherein the load is a voltage-controlled oscillator.

41. A method for providing a regulated voltage for a load, that approaches a reference voltage, comprising actions of:
generating an error voltage representing a difference between the reference voltage and the regulated voltage;
sampling the error voltage at a first clock frequency to generate a first control signal in which a noi

Assignees

• Petrov Dmitry
• Huawei Tech Co Ltd

Inventors

• Petrov Dmitry

Classifications

• H02M3/157

  with digital control · CPC title

• G05F1/56 Primary

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title