Methods for row hammer mitigation and memory devices and systems employing the same

Patent metadata

Field	Value
Publication number	US-12183383-B2
Application number	US-202318384682-A
Country	US
Kind code	B2
Filing date	Oct 27, 2023
Priority date	Oct 9, 2018
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.

First claim

What is claimed is:

1. A method, comprising:
receiving a refresh command for a bank of a dynamic random access memory (DRAM) device;
identifying a first value of a command bit in the refresh command, wherein the first value of the command bit indicates that the refresh command is a refresh management command for the bank of the DRAM device, and wherein an initial management threshold associated with the refresh management command is based on a value of a mode register of the DRAM device; and
executing the refresh management command in response to identifying the first value of the command bit in the refresh command.

2. The method of claim 1 , wherein the DRAM device comprises the mode register, the mode register operable to store the initial management threshold.

3. The method of claim 1 , further comprising:
receiving periodic refresh commands; and
executing refresh operations in response to the periodic refresh commands.

4. A method, comprising:
monitoring for an activation command issued to a bank of a dynamic random access memory (DRAM) device;
incrementing, in response to the activation command, a rolling accumulated activations (RAA) count associated with the bank of the DRAM device; and
issuing, to the DRAM device, a refresh management command for the bank of the DRAM device in response to the RAA count exceeding an initial management threshold.

5. The method of claim 4 , wherein a value of the initial management threshold is stored in a mode register of the DRAM device.

6. The method of claim 4 , further comprising:
disallowing one or more additional activation commands associated with the bank in response to the RAA count exceeding an RAA maximum value.

7. The method of claim 6 , further comprising:
permitting the one or more additional activation commands associated with the bank in response to the RAA count dropping below the RAA maximum value.

8. The method of claim 6 , wherein the RAA maximum value is greater than the initial management threshold.

9. The method of claim 4 , further comprising:
permitting one or more additional activation commands associated with the bank in response to the RAA count being less than an RAA maximum value.

10. The method of claim 4 , further comprising:
decreasing, in response to the refresh management command, the RAA count by a quantity that is based on the initial management threshold.

11. The method of claim 10 , wherein the quantity is equal to the initial management threshold.

12. The method of claim 4 , further comprising:
decreasing, in response to the refresh management command, the RAA count and one or more other RAA counts associated with one or more other banks of the DRAM device by a quantity that is based on the initial management threshold.

13. The method of claim 4 , further comprising:
decreasing, in response to the refresh management command, a plurality of RAA counts associated with each bank of a plurality of banks of the DRAM device, each RAA count of the plurality of RAA counts decreased by a quantity that is based on the initial management threshold.

14. The method of claim 4 , further comprising:
issuing periodic refresh commands associated with the bank; and
decreasing, in response to issuing a refresh command of the periodic refresh commands, the RAA count associated with the bank by a quantity that is based on the initial management threshold.

15. The method of claim 4 , wherein issuing the refresh management command comprises:
issuing, in response to the RAA count exceeding the initial management threshold, a refresh management all bank command for a plurality of banks of the DRAM device, the plurality of banks comprising the bank.

16. The method of claim 4 , wherein issuing the refresh management command comprises:
issuing, in response to the RAA count exceeding the initial management threshold, a refresh management same bank command for the bank of the DRAM device.

17. The method of claim 4 , wherein the initial management threshold is based on a value of a mode register of the DRAM device.

18. The method of claim 4 , wherein the initial management threshold comprises a maximum activation count (MAC) threshold.

19. A memory system, comprising:
a dynamic random access memory (DRAM) device; and
a controller coupled with the DRAM device and operable to:
issue one or more activation commands for a bank of the DRAM device;
increase a rolling accumulated activations (RAA) count associated with the bank of the DRAM device in response to the one or more activation commands; and
issue a refresh management command for the bank in response to the RAA count exceeding an initial management threshold; and

wherein the DRAM device is operable to:
execute the one or more activation commands associated with the bank of a plurality of banks of the DRAM device; and
receive the refresh management command for the bank in response to a quantity of the one or more activation commands.

20. The memory system of claim 19 , further comprising:
a mode register of the DRAM device, the mode register operable to store the initial management threshold.

21. The memory system of claim 19 , wherein the controller is further operable to disallow one or more additional activation commands associated with the bank in response to the RAA count exceeding an RAA maximum value.

22. The memory system of claim 21 , wherein the controller is further operable to permit the one or more additional activation commands associated with the bank in response to the RAA count dropping below the RAA maximum value.

23. The memory system of claim 21 , wherein the RAA maximum value is greater than the initial management threshold.

24. The memory system of claim 21 , wherein the controller is further operable to permit one or more additional activation commands associated with the bank in response to the RAA count being less than an RAA maximum value.

25. The memory system of claim 19 , wherein the controller is further operable to decrease, in response to issuing the refresh management command, the RAA count by a quantity that is based on the initial management threshold.

26. The memory system of claim 25 , wherein the quantity is equal to the initial management threshold.

27. The memory system of claim 19 , wherein the controller is further operable to decrease, in response to the refresh management command, the RAA count and one or more other RAA counts associated with one or more other banks of the DRAM device by a quantity that is based on the initial management threshold.

28. The memory system of claim 19 , wherein the controller is further operable to decrease, in response to the refresh management command, a plurality of RAA counts associated with each bank of the plurality of banks of the DRAM device, each RAA count of the plurality of RAA counts decreased by a quantity that is based on the initial management threshold.

29. The memory system of claim 19 , wherein the controller is further operable to:
issue periodic refresh commands associated with the bank; and
decrease, in response to issuing a refresh command of the periodic refresh commands, the RAA count associated with the bank by a quantity that is based on the initial management threshold.

30. The memory system of claim 19 , wherein, to issue the refresh management command, the control

Assignees

• Lodestar Licensing Group Llc

Inventors

• Cowles Timothy B
• Gans Dean D
• Li Jiyun
• Meier Nathaniel J
• Rooney Randall J

Classifications

• G11C11/40618 Primary

  Refresh operations over multiple banks or interleaving · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C2211/4061

  Calibration or ate or cycle tuning · CPC title