DRAM adjacent row disturb mitigation

Patent metadata

Field	Value
Publication number	US-9812185-B2
Application number	US-201615019788-A
Country	US
Kind code	B2
Filing date	Feb 9, 2016
Priority date	Oct 21, 2015
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

The invention pertains to data disturb vulnerabilities in Dynamic Random Access Memory (DRAM) integrated circuits. In particular, it pertains to mitigating attacks on a computational system by deliberate inducement of disturbs on a targeted row (also known as “row hammering”) in the system's DRAM memory. The stream of row addresses accompanying ACTIVE commands is monitored and filtered to only track addresses that occur at a dangerous rate and reject addresses that occur at less than a dangerous rate. When a tracked address poses a danger of causing a memory disturb, each row adjacent to the tracked address row is refreshed thus mitigating the danger.

First claim

What is claimed is:

1. A method for mitigating data loss in a memory array with addressable rows, wherein each addressable row requires regular refresh operations, wherein each addressable row is physically adjacent to at least one other addressable row, and wherein the memory array is coupled (i) to a decoder further coupled to address inputs, and (ii) to command circuitry further coupled to command inputs, the method comprising:
(A) monitoring the command inputs to detect row activate commands;
(B) monitoring the address inputs to detect a sequence of active row addresses, each active row address associated with a row activate command;
(C) identifying one or more detected row addresses by presenting the sequence of active row addresses to a first filter coupled to the address inputs, the first filter detecting when an active row address occurs at a more frequent rate than a predetermined maximum rate; and
(D) presenting each detected row address to a second filter coupled to the first filter, wherein:
(i) upon a first detection of a detected row address that row address is stored in a tracked address memory location, each tracked address memory location being coupled to a first associated counter and a second associated counter, each counter having a stored value,
(ii) the first associated counter and the second associated counter are both reset when the detected row address is first stored in the tracked address memory location,
(iii) upon a subsequent detection of the detected row address in the tracked memory address location the first associated counter is incremented, and
(iv) upon detection of every detected row address the second associated counter is incremented, and
(v) wherein:
if the value in any first counter exceeds a first predetermined value,
then a non-regular data loss mitigation refresh operation is performed for the one or more addressable rows physically adjacent to detected row address stored in the associated tracked memory address location.

2. The method of claim 1 ,
wherein the predetermined maximum rate is specified by data stored in one of the group consisting of: (i) a non-volatile memory and (ii) a mode register, and
wherein the predetermined maximum number of occurrences is specified by data stored in one of the group consisting of: (i) a non-volatile memory and (ii) a mode register.

3. The method of claim 1 , further comprising the step:
(E) resetting the first associated counter and the second associated counter coupled to each tracked address memory location either:
when a non-regular data loss mitigation refresh operation for each row physically adjacent to the detected row address stored in the tracked memory location is performed, or
when a regular row refresh operation for each row physically adjacent to the detected row address stored in the tracked memory location is performed.

4. The method of claim 3 ,
wherein the predetermined maximum rate is specified by data stored in one of the group consisting of: (i) a non-volatile memory and (ii) a mode register, and
wherein the predetermined maximum number of occurrences is specified by data stored in one of the group consisting of: (i) a non-volatile memory and (ii) a mode register.

5. The method of claim 3 , wherein the first filter comprises a first memory:
wherein the first memory further comprises a plurality of first data words,
wherein each of the first data words is configured to have an associated match flag,
wherein each first data word contains an active row address written in sequence in a first in/first out (FIFO) manner from the sequence of active row addresses presented to the first filter,
wherein each match flag is reset when an active row address is written into the associated first data word,
wherein the associated match flag is set for each of the first plurality of data words where the contents of the data word match the presented active row address, and
wherein the associated match flag is not set for each of the first plurality of data words where the contents of the data word do not match the presented active row address.

6. The method of claim 5 ,
wherein the predetermined maximum rate is specified by data stored in one of the group consisting of: (i) a non-volatile memory and (ii) a mode register, and
wherein the predetermined maximum number of occurrences is specified by data stored in one of the group consisting of: (i) a non-volatile memory and (ii) a mode register.

7. The method of claim 5 , wherein the second filter comprises a second memory:
wherein the second memory further comprises second data words, each second data word being a tracked address memory location, and
wherein each second data word contains a detected row address written into the second memory in a random access manner.

8. The method of claim 7 ,
wherein the predetermined maximum rate is specified by data stored in one of the group consisting of: (i) a non-volatile memory and (ii) a mode register, and
wherein the predetermined maximum number of occurrences is specified by data stored in one of the group consisting of: (i) a non-volatile memory and (ii) a mode register.

9. The method of claim 7 , further comprising the steps:
(F) selecting one of the plurality of second data words, the selected second data word being eligible to be selected if the stored value of its associated second counter is greater than a second predetermined value;
(G) writing a detected row address into the selected second data word when the detected row address does not match the contents of any of the tracked address memory locations in the plurality of second data words is presented to the second filter;
(H) resetting first counter associated with the selected one of the second data words; and
(I) resetting second counter associated with the selected one of the second data words.

10. The method of claim 3 , wherein the second filter comprises a second memory:
wherein the second memory further comprises second data words, each second data word being a tracked address memory location,
wherein each second data word contains a detected row address written into the second memory in a random access manner.

11. The method of claim 10 ,
wherein the predetermined maximum rate is specified by data stored in one of the group consisting of: (i) a non-volatile memory and (ii) a mode register, and
wherein the predetermined maximum number of occurrences is specified by data stored in one of the group consisting of: (i) a non-volatile memory and (ii) a mode register.

12. The method of claim 10 , further comprising the steps:
(F) selecting one of the plurality of second data words, the selected second data word being eligible to be selected if the stored value of its associated second counter is greater than a second predetermined value;
(G) writing a detected row address into the selected second data word when the detected row address does not match the contents of any of the tracked address memory locations in the plurality of second data words is presented to the second filter;
(H) resetting first counter associated with the selected one of the second data words; and
(I) resetting second counter associated with the selected one of the second data words.

13. The method of claim 1 , wherein the first filter comprises a first memory:
wherein the first memory further comprises a plurality of first data words,
wherein each of the first data words is configured to have an associated match flag,
wherein each first data word contains an active row address written in sequence in a first in/first out (FIFO) manner from the sequence of active row addresse

Assignees

• Invensas Corp

Inventors

• Fisch David Edward
• Plants William C

Classifications

• G11C11/406 Primary

  Management or control of the refreshing or charge-regeneration cycles · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C11/4078 Primary

  Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52) · CPC title

• G11C7/24

  Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells · CPC title

• G11C29/789

  using non-volatile cells or latches · CPC title