Apparatuses and methods for configurable memory array bank architectures

Patent metadata

Field	Value
Publication number	US-12182397-B2
Application number	US-202318326303-A
Country	US
Kind code	B2
Filing date	May 31, 2023
Priority date	Jun 28, 2018
Publication date	Dec 31, 2024
Grant date	Dec 31, 2024

Abstract

Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.

First claim

What is claimed is:

1. An apparatus comprising:
a mode register configured to store a value to set a bank architecture from a plurality of bank architectures, wherein the value in the mode register is configured to be switched by changing a frequency set point between a plurality of frequency set points;
a memory array, wherein memory banks of the memory array are configured in a bank group mode when the value comprises a first value and the memory banks of the memory array are configured in a bank mode when the value comprises a second value;
a plurality of data busses coupled to the memory array;
a plurality of external data terminals; and
a plurality of data paths coupled between the plurality of data buses and the plurality of external terminals.

2. The apparatus of claim 1 , wherein a width of a data path of the plurality of data paths and a width of a data bus of the plurality of data busses are a same width for the bank group mode and the bank mode.

3. The apparatus of claim 2 , wherein the same width comprises 128 bits.

4. The apparatus of claim 1 , wherein the plurality of external data terminals comprises sixteen external data terminals.

5. The apparatus of claim 1 , wherein the plurality of external data terminals comprises eight external data terminals.

6. The apparatus of claim 1 , wherein a width of a data path of the plurality of data paths and a width of a data bus of the plurality of data busses are a same width for the bank group mode, and wherein a width of the data path of the plurality of data paths and a width of the data bus of the plurality of data busses are different for the bank mode, wherein for the bank mode, the width of the data bus of the plurality of data busses comprises 128 bits and the width of the data path of the plurality of data paths comprises 256 bits.

7. A method comprising:
receiving a clock signal at a memory;
receiving a mode register write command and a value to be written to a mode register of the memory;
responsive to the mode register write command, writing the value to the mode register to set a frequency set point of a plurality of frequency set points of the memory;
receiving a first read command and a first address; and
receiving a second read command and a second address,
providing first data associated with the first read command and providing second data associated with the second read command when the second read command is received at least a number of clock cycles after the first read command, the number of clock cycles based, at least in part, on a bank architecture set in the memory wherein the bank architecture is based, at least in part, on the frequency set point.

8. The method of claim 7 , wherein the number of clock cycles is further based on a burst length of the bank architecture.

9. The method of claim 8 , wherein the bank architecture is a bank group mode, and the number of clock cycles is at least two clock cycles when the burst length is sixteen, and the number of clock cycles is at least four clock cycles when the burst length is thirty-two.

10. The method of claim 7 , wherein the number of clock cycles is further based on whether the first address and the second address are in a same bank group.

11. The method of claim 10 , wherein the number of clock cycles is at least four clock cycles when the first address and the second address are for the same back group, and the number of clock cycles is at least two clock cycles when the first address and the second address are for different bank groups.

12. The method of claim 7 , wherein the number of clock cycles is at least two clock cycles.

13. The method of claim 7 , wherein the number of clock cycles is at least four clock cycles.

14. The method of claim 7 , further comprising:
receiving a third read command;
providing first data responsive to the first read command and providing second data responsive to the second read command;
providing third data responsive to the third read command; and
providing fourth data responsive to the third read command at least two clock cycles of the clock signal after providing the third data.

15. An apparatus comprising:
a clock circuit configured to receive an external clock signal;
a command decoder configured to receive a first read command and a second read command; an address decoder configured to receive a first address and a second address associated with the first and second read commands;
a mode register configured to store a first value to set a bank architecture from a plurality of bank architectures, wherein the plurality of bank architectures comprises a bank mode and a bank group mode and further configured to store a second value to set a frequency set point from a plurality of frequency set points, wherein the first value is configured to be changed by changing the second value; and
a memory array configured in one of the plurality of bank architectures based on the value, wherein the memory array is further configured to provide first data responsive to the first read command and to provide second data responsive to the second read command when the second read command is received at least a number of clock cycles after the first read command, wherein the number of clock cycles is based at least in part, on the bank architecture of the memory array.

16. The apparatus of claim 15 , wherein the number of clock cycles is at least two clock cycles when a burst length is sixteen and the number of clock cycles is at least four clock cycles when the burst length is thirty-two.

17. The apparatus of claim 15 , wherein when the bank architecture comprises the bank group mode, and wherein the number of clock cycles is at least four clock cycles when the first address and the second address are for the same bank group and the number of clock cycles is at least two clock cycles when the first address and the second address are for different bank groups.

18. The apparatus of claim 15 , wherein the number of clock cycles is at least two clock cycles or at least four clock cycles.

19. The apparatus of claim 15 , wherein when the bank architecture comprises the bank group mode and the first and second read commands are for different bank groups, the memory is configured to provide sixteen bits of data from a first bank group followed by sixteen bits of data from a second bank group.

20. The apparatus of claim 19 , wherein when a burst length is thirty-two bits, the memory is further configured to provide a second sixteen bits of data from the first bank group followed by another sixteen bits of data from the second bank group.

Assignees

• Micron Technology Inc

Inventors

• Gans Dean D
• Saito Shunichi

Classifications

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F2212/1012

  Design facilitation · CPC title

• G06F12/10

  Address translation · CPC title

• G06F2212/7202

  Allocation control and policies · CPC title