Internal consecutive row access for long burst length

Patent metadata

Field	Value
Publication number	US-2016378366-A1
Application number	US-201514749605-A
Country	US
Kind code	A1
Filing date	Jun 24, 2015
Priority date	Jun 24, 2015
Publication date	Dec 29, 2016
Grant date	—

Abstract

A memory device executes internal operations to provide a programmable burst length. The memory device includes multiple banks that are independent and separately addressable. The memory device selects a number of banks to operate in burst sequence, where all selected banks operate on a command sent from an associated memory controller. In response to receiving the access command, the memory device generates multiple internal operations to cause all selected memory banks to execute the access command, without requiring multiple commands from the memory controller.

First claim

What is claimed is:

1 . A method for memory device access, comprising:
dynamically selecting a number of bank groups to operate in a burst sequence, from among multiple independent bank groups that are separately addressable, where each selected bank group is to operate on a command received from an associated memory controller; receiving a single access command from the associated memory controller; and generating multiple internal operations within the memory device to cause all selected bank groups to execute the access command.

2 . The method of claim 1 , wherein selecting the number of bank groups comprises selecting the number of bank groups in response to a setting in a mode register of the memory device.

3 . The method of claim 1 , wherein selecting the number of bank groups comprises selecting the number of bank groups in response to an on-the-fly command from the memory controller indicating a desired burst length.

4 . The method of claim 1 , wherein selecting the number of bank groups comprises selecting from among multiple programmable burst lengths.

5 . The method of claim 1 , wherein receiving the single access command comprises receiving a single Activate and CAS (column address select) sequence; and wherein generating the multiple internal operations comprises applying the Activate and CAS sequence to all selected bank groups.

6 . The method of claim 5 , wherein the Activate and CAS sequence comprise a Read command.

7 . The method of claim 5 , wherein the Activate and CAS sequence comprise a Write command.

8 . The method of claim 1 , wherein generating the multiple internal operations further comprises monitoring bank group operations via a bank group counter internal to the memory device.

9 . The method of claim 8 , wherein generating the multiple internal operations comprises performing the operations in order of sequential bank group address.

10 . The method of claim 8 , wherein generating the multiple internal operations comprises performing the operations in non-sequential order with interleaved bank group addresses.

11 . A memory device in a memory subsystem, comprising:
multiple banks of memory, wherein bank separately addressable from other banks; I/O (input/output) hardware configured to receive an access command, the access command to be generated by an associated memory controller; and control logic within the memory device to dynamically select a number of banks to operate in a burst sequence, and generate multiple internal operations within the memory device in response to the access command to cause all selected banks to execute the access command.

12 . The memory device of claim 11 , wherein the multiple banks of memory are organized as independent bank groups each including one or more banks, wherein all banks in a bank group are addressed together.

13 . The memory device of claim 11 , further comprising a mode register to store settings that control operation of the memory device, wherein the control logic is to select the number of banks including reading a burst mode setting in the mode register, and selecting the number of banks in response to the burst mode setting.

14 . The memory device of claim 11 , wherein the control logic is to select the number of banks in response to an on-the-fly command from the memory controller indicating a desired burst length.

15 . The memory device of claim 11 , wherein the I/O hardware is to receive a single Activate and CAS (column address select) sequence; and wherein the control logic is to apply the Activate and CAS sequence to all selected banks.

16 . The memory device of claim 11 , further comprising a counter internal to the memory device, and wherein the control logic is to monitor bank operations via the counter, including tracking sequencing of operations for the banks.

17 . An electronic device with a memory subsystem, comprising:
a memory controller; a memory device to interface with the memory controller, the memory device including multiple bank groups, each separately addressable;
I/O (input/output) hardware to receive an access command from the memory controller;
control logic within the memory device to dynamically select a number of bank groups to operate in a burst sequence, and generate multiple internal operations within the memory device in response to the access command to cause all selected bank groups to execute the access command; and
a touchscreen display coupled to generate an interactive display based on data accessed from the memory device.

18 . The electronic device of claim 17 , the memory device further including a mode register to store settings that control operation of the memory device, wherein the control logic is to select the number of bank groups including reading a burst mode setting in the mode register, and selecting the number of bank groups in response to the burst mode setting.

19 . The electronic device of claim 17 , wherein the I/O hardware is to receive a single Activate and CAS (column address select) sequence from the memory controller; and wherein the control logic is to apply the Activate and CAS sequence to all selected bank groups.

20 . The electronic device of claim 17 , the memory device further including an internal counter, wherein the control logic is to monitor bank group operations via the counter, including tracking sequencing of operations for the bank groups.

Assignees

• Intel Corp

Inventors

• Tomishima Shigeki
• Lu Shih-Lien L
• Bains Kuljit S

Classifications

• G11C7/08

  Control thereof · CPC title

• G11C11/409

  Read-write [R-W] circuits · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title

• G11C7/1072 Primary

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G11C7/1021

  Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address · CPC title