Apparatuses and methods for configurable memory array bank architectures

Patent metadata

Field	Value
Publication number	US-10788985-B2
Application number	US-201916452424-A
Country	US
Kind code	B2
Filing date	Jun 25, 2019
Priority date	Jun 28, 2018
Publication date	Sep 29, 2020
Grant date	Sep 29, 2020

Abstract

Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.

First claim

What is claimed is:

1. An apparatus, comprising:
a mode register configured to store information related to bank architecture; and
a memory array including a plurality of memory banks, the plurality of memory banks configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register, wherein the plurality of memory banks of the memory array includes a first half-bank and a second half-bank, and for a bank architecture with bank group mode configuration data is provided from both the first half-bank and the second half-bank when the plurality of memory banks are accessed.

2. The apparatus of claim 1 wherein the bank group mode configuration comprises n banks and m bank groups, wherein each of the n banks includes memory banks of the plurality of memory banks and each of the m bank groups includes memory banks included with each of the n banks, wherein n and m are both non-zero whole numbers.

3. The apparatus of claim 2 wherein each of the bank groups transfer data to and from a data path on a respective data bus.

4. The apparatus of claim 2 wherein n is four and m is four.

5. The apparatus of claim 1 wherein the bank architecture comprises a bank mode configuration.

6. The apparatus of claim 5 wherein the bank mode configuration comprises p banks, each of the p banks including q memory banks of the plurality of memory banks, wherein p and q are both non-zero whole numbers.

7. The apparatus of claim 6 wherein p is eight and q is four.

8. The apparatus of claim 6 wherein p is sixteen and q is two.

9. The apparatus of claim 1 wherein an amount of data for data prefetch of the memory array is based at least in part on the bank architecture.

10. An apparatus, comprising:
external data terminals;
a data path configured to provide data to and from the external data terminals; and
a plurality of data busses configured to transfer data between the plurality of memory banks and the data path, wherein each of the plurality of data busses has a first data width and wherein each of the data paths has a second data width that is different from the first data width;
a command decoder configured to receive and decode an access command and provide internal signals responsive thereto;
an address decoder configured to receive an address associated with the access command and provide decoded address signals responsive thereto;
a mode register configured to be programmed with a value for a bank architecture setting; and
a memory array including a plurality of memory banks, the plurality of memory banks configured to be accessed responsive to the internal signals, wherein the plurality of memory banks are arranged according to a bank architecture that is selected at least in part on the bank architecture setting, and wherein the address decoder is configured to map at least a portion of the decoded address signals to the plurality of memory banks based on the selected bank architecture to access the plurality of memory banks according to the selected bank architecture.

11. The apparatus of claim 10 wherein the bank architecture is selected from at least a bank architecture with a bank group mode configuration and a bank architecture with a bank mode configuration.

12. The apparatus of claim 10 wherein the data path comprises read/write amplifiers and an input/output circuit.

13. The apparatus of claim 10 wherein the first data width is one-half the second data width.

14. The apparatus of claim 10 wherein the plurality of memory banks comprises a first half-bank and a second half-bank, and data is provided from both the first half-bank and the second half-bank when the plurality of memory banks are accessed.

15. The apparatus of claim 10 wherein the address decoder is configured to map decoded bank address signals according to the selected bank architecture.

16. An apparatus, comprising:
a controller configured to provide access commands and associated addresses;
a plurality of busses coupled to the controller and configured to provide signals and clocks to and from the controller; and
a memory system coupled to the plurality of busses and configured to receive the access commands and the associated addresses, the memory system including a plurality of memory banks and a mode register, the mode register configured to be programmed with first values corresponding to a bank architecture setting for a first frequency set point and programmed with second values corresponding to a bank architecture setting for a second frequency set point,
wherein the controller accesses the plurality of memory banks of the memory according to a selected bank architecture that is based on the value corresponding to the bank architecture setting in the mode register.

17. The apparatus of claim 16 wherein the selected bank architecture comprises at least one of a bank architecture with a bank group mode configuration and a bank architecture with a bank mode configuration.

18. The apparatus of claim 16 wherein the mode register is further configured to be programmed with a value corresponding to a burst length setting, and wherein the controller is further accesses the plurality of memory banks of the memory according to a burst length that is based on the value corresponding to a burst length setting in the mode register.

19. A method, comprising:
receiving an access command and associated address;
accessing a plurality of memory banks of a memory array, wherein the plurality of memory banks are arranged in a bank architecture; and
providing to external data terminals data from memory locations in the plurality of memory banks that correspond to the associated address, wherein the data from the memory locations are provided to the external terminals having a timing based at least in part on the bank architecture of the plurality of memory banks,
wherein for a bank architecture with bank group mode configuration, data for an access command for a first burst length is provided to the external data terminals in one hit group and data for the access command for a second burst length is provided to the external data terminals split into multiple bit groups separated by a time gap.

20. The method of claim 19 wherein for the first burst length data for a first access command to a first bank group and data for a second access command to the first bank group are provided with a time gap therebetween.

21. The method of claim 19 wherein for the bank group mode configuration a minimum timing for first and second access commands to a same bank group is greater than a minimum timing for first and second access commands to different bank groups.

22. The method of claim 19 wherein the bank architecture comprises a bank mode configuration and wherein data for a first access command to a first bank and data for a second access command to the first bank are provided without a time gap.

23. The method of claim 19 wherein the bank architecture comprises a bank mode configuration and wherein a minimum timing for first and second access commands to a same bank group is the same as a minimum timing for first and second access commands to different bank groups.

24. A method, comprising:
receiving an access command and associated address;
accessing a plurality of memory banks of a memo array, wherein the plurality of memory banks are arranged in a bank architecture; and
providing to external data te

Assignees

• Micron Technology Inc

Inventors

• Gans Dean D
• Saito Shunichi

Classifications

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C7/10 Primary

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G06F2212/7202

  Allocation control and policies · CPC title

• G06F12/0246

  in block erasable memory, e.g. flash memory · CPC title

• G11C7/1048

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title