Printed wiring board

US12177973B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12177973-B2
Application numberUS-202017922872-A
CountryUS
Kind codeB2
Filing dateMay 20, 2020
Priority dateMay 20, 2020
Publication dateDec 24, 2024
Grant dateDec 24, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A printed wiring board includes a base layer having insulating properties, a first conductive layer directly or indirectly stacked on the base layer front surface, and including a copper foil, a second conductive layer directly or indirectly stacked on the base layer back surface, and including a copper foil, a stacked body for a via hole, the stacked body being stacked on an inner periphery and a bottom of a connection hole that extends through the first conductive layer and the base layer in a thickness direction, and being configured to electrically connect the first conductive layer and the second conductive layer to each other, and having an electroless copper plating layer. Each copper foil contains a copper crystal grain oriented in a plane orientation, and an average crystal grain size of copper of each copper foil is 10 μm or greater, the electroless copper plating layer includes palladium.

First claim

Opening claim text (preview).

The invention claimed is: 1. A printed wiring board comprising: a base layer having insulating properties; a first conductive layer directly or indirectly stacked on a front surface of the base layer, and including a copper foil; a second conductive layer directly or indirectly stacked on a back surface of the base layer, and including a copper foil; a stacked body for a via hole, the stacked body being stacked on an inner periphery and a bottom of a connection hole that extends through the first conductive layer and the base layer in a thickness direction, and being configured to electrically connect the first conductive layer and the second conductive layer to each other, wherein the stacked body for the via hole has an electroless copper plating layer that is stacked on the inner periphery and the bottom of the connection hole, and an electrolytic copper plating layer that is stacked on a surface of the electroless copper plating layer, wherein each copper foil contains a copper crystal grain oriented in a (100) plane orientation, and an average crystal grain size of copper of each copper foil is 10 μm or greater, wherein the electroless copper plating layer includes palladium, and wherein a stacking amount of the palladium per unit area of a surface of each copper foil is 0.03 μg/cm 2 to 0.15 μg/cm 2 , the surface of each copper foil facing the electroless copper plating layer. 2. The printed wiring board according to claim 1 , wherein a proportion of an area of the copper crystal grain oriented in the (100) plane orientation existing in the surface of each copper foil with respect to an area of the surface of each copper foil is 50% or greater. 3. The printed wiring board according to claim 1 , wherein the stacking amount of the palladium per unit area of the surface of each copper foil is 0.05 μg/cm 2 to 0.10 μg/cm 2 . 4. The printed wiring board according to claim 3 , wherein a proportion of an area of the copper crystal grain oriented in the (100) plane orientation existing in the surface of each copper foil with respect to an area of the surface of each copper foil is 50% or greater. 5. The printed wiring board according to claim 1 , wherein an average thickness of the electroless copper plating layer is 0.05 μm to 1.0 μm.

Assignees

Inventors

Classifications

  • Blind vias, i.e. vias having one side closed · CPC title

  • Metal foils · CPC title

  • Via connections; Lands around holes or via connections (H05K1/112 takes precedence) · CPC title

  • with use of organic or inorganic compounds other than metals, first · CPC title

  • Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating · CPC title

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Frequently asked questions

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What does patent US12177973B2 cover?
A printed wiring board includes a base layer having insulating properties, a first conductive layer directly or indirectly stacked on the base layer front surface, and including a copper foil, a second conductive layer directly or indirectly stacked on the base layer back surface, and including a copper foil, a stacked body for a via hole, the stacked body being stacked on an inner periphery an…
Who is the assignee on this patent?
Sumitomo Electric Industries, Sumitomo Electric Printed Circuits Inc
What technology area does this patent fall under?
Primary CPC classification H05K1/09. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 24 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).