Printed circuit board

Patent metadata

Field	Value
Publication number	US-11877397-B2
Application number	US-202017605939-A
Country	US
Kind code	B2
Filing date	May 15, 2020
Priority date	May 15, 2019
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

The printed circuit board includes, a first conductive layer including copper foil, an insulating base layer, and a second conductive layer including copper foil in this order, and includes a via-hole laminate that is stacked on an inner circumference and a bottom of a connection hole extending through the first conductive layer and the base layer in a thickness direction. The via-hole laminate has an electroless copper plating layer stacked on the connection hole and an electrolytic copper plating layer stacked on the electroless copper plating layer. The copper foil has copper crystal grains oriented in a (100) plane orientation, and an average crystal grain size of copper of 10 μm or more. The electroless copper plating layer includes palladium and tin, and an amount of the palladium stacked per unit area of a surface of the copper foil is 0.18 μg/cm 2 or more and 0.40 μg/cm 2 or less.

First claim

The invention claimed is:

1. A printed circuit board comprising:
an insulating base layer;
a first conductive layer that is stacked on a front surface of the base layer either directly or indirectly and that includes copper foil;
a second conductive layer that is stacked on a back surface of the base layer either directly or indirectly and that includes copper foil; and
a via-hole laminate that is stacked on an inner circumference and a bottom of a connection hole extending through the first conductive layer and the base layer in a thickness direction and that electrically connects the first conductive layer to the second conductive layer,
wherein the via-hole laminate has an electroless copper plating layer that is stacked on the inner circumference and the bottom of the connection hole and an electrolytic copper plating layer stacked on a surface of the electroless copper plating layer,
the copper foil contains copper crystal grains oriented in a (100) plane orientation, and an average crystal grain size of copper of the copper foil is 10 μm or more,
the electroless copper plating layer includes palladium and tin, and
an amount of the palladium stacked per unit area of a surface of the copper foil is 0.18 μg/cm 2 or more and 0.40 μg/cm 2 or less.

2. The printed circuit board according to claim 1 , wherein an amount of the tin stacked per unit area of the surface of the copper foil is 0.05 μg/cm 2 or more and 1.20 μg/cm 2 or less.

3. The printed circuit board according to claim 1 , wherein a ratio of an area of copper crystal grains oriented in the (100) plane orientation and present on the surface of the copper foil relative to an area of the surface of the copper foil is 50% or more.

4. The printed circuit board according to claim 1 , wherein the amount of the palladium stacked per unit area of the surface of the copper foil is 0.18 μg/cm 2 or more and 0.35 μg/cm 2 or less.

5. The printed circuit board according to claim 1 , wherein a ratio of an area of copper crystal grains oriented in the (100) plane orientation and present on the surface of the copper foil relative to an area of the surface of the copper foil is 60% or more.

6. The printed circuit board according to claim 1 , wherein the electroless copper plating layer has an average thickness of 0.01 μm or more and 1.0 μm.

Assignees

• Sumitomo Electric Industries
• Sumitomo Electric Printed Circuits Inc

Inventors

• Motomura Junichi
• Nitta Koji
• Sakai Shoichiro
• Sogabe Mari
• Tsubokura Mitsutaka
• Tsuchiko Akira
• Iwamoto Masashi

Classifications

• H05K1/09 Primary

  Use of materials for the {conductive, e.g. } metallic pattern · CPC title

• C25D3/38

  of copper · CPC title

• H05K2201/0355

  Metal foils · CPC title

• H05K3/427 Primary

  initial plating of through-holes in metal-clad substrates · CPC title

• H05K2201/09509

  Blind vias, i.e. vias having one side closed · CPC title