Method for manufacturing multilayer wiring substrate

Patent metadata

Field	Value
Publication number	US-10076044-B2
Application number	US-201415027756-A
Country	US
Kind code	B2
Filing date	Sep 24, 2014
Priority date	Oct 9, 2013
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

The present invention is a method for manufacturing a multilayer wiring board having (1) a step of providing with a hole for a via hole from a metal foil for an upper layer wiring pattern to an inner layer wiring pattern by using a conformal method or a direct laser method, and (2) a step of forming a via hole by forming electrolytic filling plating layers in the hole for a via hole, wherein the formation of the electrolytic filling plating layers in the step (2) is carried out by repeating change in electric current density of temporarily decreasing the electric current density of electrolytic filling plating in the middle of the electrolytic filling plating and then increasing it again, two or more times before the electrolytic filling plating layers block an opening of the hole for a via hole.

First claim

The invention claimed is:

1. A method for manufacturing a multilayer wiring board, comprising:
(1) a step of integrally laminating an inner layer material with an inner layer wiring pattern formed thereon, an insulating layer, and a metal foil for an upper layer wiring pattern, and providing the metal foil for an upper layer wiring pattern and the insulating layer with a hole for a via hole from the metal foil for an upper layer wiring pattern to the inner layer wiring pattern, an overhang of the metal foil for an upper layer wiring pattern formed at an opening of the hole for a via hole, and lower space formed between the overhang of the metal foil and an inside wall of the hole for a via hole by using a conformal method or a direct laser method;
(2) a step of forming a base electroless plating layer within the hole for a via hole and on the metal foil for an upper layer wiring pattern, and then forming a via hole that connects the metal foil for an upper layer wiring pattern and the inner layer wiring pattern, by forming electrolytic filling plating layers; and
(3) a step of wiring the metal foil for an upper layer wiring pattern after the formation of the electrolytic filling plating layers to form the upper layer wiring pattern,
wherein the formation of the electrolytic filling plating layers in the step (2) is carried out by repeating change in electric current density of temporarily decreasing the electric current density of electrolytic filling plating in the middle of the electrolytic filling plating, and then increasing it again, two or more times before the electrolytic filling plating layers block the opening of the hole for a via hole.

2. The method for manufacturing a multilayer wiring board according to claim 1 ,
wherein in the step (2), the change in electric current density of temporarily decreasing the electric current density of electrolytic filling plating and then increasing it again is repeated two or more times before the electrolytic filling plating layers block the opening of the hole for a via hole, whereby the electrolytic filling plating layers are formed in a form following the inside wall and the bottom face of the hole for a via hole.

3. The method for manufacturing a multilayer wiring board according to claim 1 ,
wherein in the step (2), the timing of temporarily decreasing the electric current density of electrolytic filling plating is before the electrolytic filling plating fills the lower space between the overhang of the metal foil for an upper layer wiring pattern formed at the opening of the hole for a via hole and the inside wall of the hole for a via hole, and a plating void is formed.

4. The method for manufacturing a multilayer wiring board according to claim 1 ,
wherein in the step (2), the rate of decrease in electric current density in temporarily decreasing the electric current density of electrolytic filling plating in the middle of the electrolytic filling plating is 50% or more of that immediately before the decrease.

5. The method for manufacturing a multilayer wiring board according to claim 1 ,
wherein in the step (2), the electric current density in temporarily decreasing the electric current density of electrolytic filling plating in the middle of the electrolytic filling plating and then increasing it again is equal to or larger than the electric current density immediately before the temporal decrease.

Assignees

• Hitachi Chemical Co Ltd

Inventors

• Yoshida Nobuyuki

Classifications

• H05K3/4652

  Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern (H05K3/4647 takes precedence) · CPC title

• H05K2203/1184

  Underetching, e.g. etching of substrate under conductors or etching of conductor under dielectrics; Means for allowing or controlling underetching · CPC title

• H05K3/0035

  of blind holes, i.e. having a metal layer at the bottom · CPC title

• H05K3/0026

  by laser ablation · CPC title

• H05K2201/0355

  Metal foils · CPC title