Backplane and method for manufacturing the same, backlight module, and display apparatus

Patent metadata

Field	Value
Publication number	US-12176333-B2
Application number	US-202117789848-A
Country	US
Kind code	B2
Filing date	Jun 24, 2021
Priority date	Jun 24, 2021
Publication date	Dec 24, 2024
Grant date	Dec 24, 2024

Abstract

A backplane includes a substrate, a circuit structure layer, a reflective layer, a plurality of electronic devices and a plurality of encapsulation portions. Each encapsulation portion covers an electronic device in the plurality of electronic devices. At least one first conductive line includes a first linear extending portion, a second linear extending portion and a third linear extending portion that are sequentially connected. Orthographic projections of the first linear extending portion, the second linear extending portion, the third linear extending portion and an encapsulation portion in the plurality of encapsulation portions on the substrate are respectively a first orthographic projection, a second orthographic projection, a third orthographic projection and a fourth orthographic projection. The first orthographic projection is located within the fourth orthographic projection, the second orthographic projection is partially overlapped with the fourth orthographic projection, and the third orthographic projection is located outside the fourth orthographic projection.

First claim

What is claimed is:

1. A backplane, comprising:
a substrate;
a circuit structure layer located on a side of the substrate;
a reflective layer located on a side of the circuit structure layer away from the substrate, the reflective layer including a plurality of first through holes arranged at intervals;
a plurality of electronic devices, each electronic device being located in a first through hole in the plurality of first through holes, and the plurality of electronic devices being electrically connected to the circuit structure layer; and
a plurality of encapsulation portions, each encapsulation portion covering an electronic device in the plurality of electronic devices;
wherein a conductive layer in the circuit structure layer farthest from the substrate includes a plurality of first conductive lines, and at least one first conductive line includes a first linear extending portion, a second linear extending portion and a third linear extending portion that are sequentially connected; an orthographic projection of the first linear extending portion on the substrate is a first orthographic projection, an orthographic projection of the second linear extending portion on the substrate is a second orthographic projection, an orthographic projection of the third linear extending portion on the substrate is a third orthographic projection, and an orthographic projection of an encapsulation portion in the plurality of encapsulation portions on the substrate is a fourth orthographic projection;
the first orthographic projection is located within the fourth orthographic projection, the second orthographic projection is partially overlapped with the fourth orthographic projection, and the third orthographic projection is located outside the fourth orthographic projection;
two endpoints of the fourth orthographic projection that are farthest from each other in a width direction of the second linear extending portion are first endpoints; and
a distance between the second orthographic projection and each of first reference lines, which respectively pass through the first endpoints and are parallel to the second linear extending portion, is not less than half of a line width of the second linear extending portion.

2. The backplane according to claim 1 , wherein the distance between the second orthographic projection and each of the first reference lines, which respectively pass through the first endpoints and are parallel to the second linear extending portion, is greater than or equal to 0.15 mm.

3. The backplane according to claim 1 , wherein two endpoints of the fourth orthographic projection that are farthest from each other in a width direction of the first linear extending portion are second endpoints; and
a distance between the first orthographic projection and each of second reference lines, which respectively pass through the second endpoints and are parallel to the first linear extending portion, is not less than half of a line width of the first linear extending portion; or the distance between the first orthographic projection and each of the second reference lines, which respectively pass through the second endpoints and are parallel to the first linear extending portion, is not less than half of the line width of the first linear extending portion and greater than or equal to 0.15 mm.

4. The backplane according to claim 1 , wherein a minimum distance between the third orthographic projection and the fourth orthographic projection is not less than half of a line width of the third linear extending portion; or the minimum distance between the third orthographic projection and the fourth orthographic projection is not less than half of the line width of the third linear extending portion and greater than or equal to 0.15 mm.

5. The backplane according to claim 1 , wherein
the at least one first conductive line further includes a first connection portion connecting the first linear extending portion and the second linear extending portion, and a second connection portion connecting the second linear extending portion and the third linear extending portion; and
an orthographic projection of the first connection portion on the substrate is located within the fourth orthographic projection, and an orthographic projection of the second connection portion on the substrate is located outside the fourth orthographic projection.

6. The backplane according to claim 5 , wherein
a minimum distance between the orthographic projection of the first connection portion on the substrate and the fourth orthographic projection is greater than or equal to 0.25 mm; and/or
a minimum distance between the orthographic projection of the second connection portion on the substrate and the fourth orthographic projection is greater than or equal to 0.25 mm.

7. The backplane according to claim 1 , wherein a shape of the fourth orthographic projection is a circle or substantially a circle; wherein
a radius of the circle is greater than or equal to 1.25 mm, or is less than or equal to 1.0 mm.

8. The backplane according to claim 1 , wherein a line width of the first linear extending portion is less than or equal to 0.2 mm;
the line width of the second linear extending portion is less than or equal to 0.2 mm; and
a line width of the third linear extending portion is less than or equal to 0.2 mm; and/or
an extending direction of the first linear extending portion is perpendicular to an extending direction of the second linear extending portion; and/or the extending direction of the second linear extending portion is perpendicular to an extending direction of the third linear extending portion.

9. The backplane according to claim 1 , further comprising:
a plurality of reflective portions, each reflective portion covering an edge of the first through hole, and the reflective portion defining a second through hole in the first through hole; and the electronic device located in the first through hole being located in the second through hole.

10. The backplane according to claim 1 , wherein the plurality of electronic devices include at least one light-emitting device and at least one driver chip.

11. The backplane according to claim 1 , wherein the circuit structure layer includes two conductive layers, a conductive layer in the two conductive layers away from the substrate is a first conductive layer, and another conductive layer in the two conductive layers proximate to the substrate is a second conductive layer; the first conductive layer includes the plurality of first conductive lines, and the second conductive layer includes a plurality of second conductive lines; and
the circuit structure layer further includes:
a first insulating layer located between the first conductive layer and the second conductive layer; and
a first transition layer located between the second conductive layer and the first insulating layer.

12. The backplane according to claim 11 , further comprising:
a second transition layer located between the substrate and the second conductive layer;
a second insulating layer located between the first conductive layer and the reflective layer; and
a third transition layer located between the first conductive layer and the second insulating layer.

13. A backlight module, comprising:
the backplane according to claim 1 , the plurality of electronic devices in the backplane include a plurality of light-emitting devices.

14. The backlight module according to claim 13 , further comprising:
a diffusion plate located on a light-emitting side of the backplane;
a quantum dot film located on a side of the diffusion plate away from th

Assignees

• Hefei Boe Optoelectronics Tech
• Boe Technology Group Co Ltd

Inventors

• Tang Hai
• Geng Xiaolin
• Gao Liang
• Zhang Shubai
• Qin Jianwei

Classifications

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10H29/0363

  of optical field-shaping means · CPC title