Multi-voltage complementary metal oxide semiconductor integrated circuits based on always-on N-well architecture

Patent metadata

Field	Value
Publication number	US-9905560-B2
Application number	US-201514983796-A
Country	US
Kind code	B2
Filing date	Dec 30, 2015
Priority date	May 27, 2015
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

Examples of multi-voltage (MV) complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) based on always-on N-well architecture are described. A MV CMOS IC may include first CMOS cells, second CMOS cells, N-wells and always-on taps. Each first CMOS cell may have a supply terminal configured to receive a local supply voltage, and an N-well (NW) terminal configured to receive a global supply voltage. The second CMOS cells may include always-on CMOS cells. Each second CMOS cell may have a supply terminal configured to receive the global supply voltage, and an NW terminal configured to receive the global supply voltage. The NW terminal of at least one of the second CMOS cells and the NW terminal of at least one of the first CMOS cells may be formed in a first N-well of the one or more N-wells.

First claim

What is claimed is:

1. A multi-voltage (MV) complementary metal oxide semiconductor (CMOS) integrated circuit (IC), comprising:
a plurality of first CMOS cells, each of the plurality of first CMOS cells having a supply terminal configured to receive a local supply voltage of a first voltage level and a N-well (NW) terminal configured to receive a global supply voltage of a second voltage level different than the first voltage level;
a plurality of second CMOS cells, each of the plurality of second CMOS cells having a supply terminal configured to receive the global supply voltage and a NW terminal configured to receive the global supply voltage, the second CMOS cells comprising always-on (AON) cells;
one or more N-wells; and
one or more always-on taps (ATAPs),
wherein a first N-well of the one or more N-wells is biased at the second voltage level by receiving the global supply voltage through the NW terminal of at least one of the plurality of first CMOS cells and the NW terminal of at least one of the plurality if second CMOS cells,
wherein the first N-well is further biased at the second voltage level by receiving the global supply voltage through the one or more ATAPs disposed in the first N-well, and
wherein each of the plurality of first CMOS cells has no terminal other than the NW terminal thereof that receives the global supply voltage.

2. The MV CMOS IC of claim 1 , wherein the plurality of the first CMOS cells and the plurality of the second CMOS cells are configured to receive the global supply voltage throughout an entire period of operation, and wherein the plurality of the first CMOS cells are also configured to receive the local supply voltage for a portion of but not the entire period of operation.

3. The MV CMOS IC of claim 1 , wherein each NW terminal of the plurality of second CMOS cells and each NW terminal of the plurality of first CMOS cells comprise the first N-well.

4. The MV CMOS IC of claim 3 , wherein the one or more N-wells comprise a single continuous N-well.

5. The MV CMOS IC of claim 1 , wherein each of the plurality of first CMOS cells comprises a p-n junction between the respective supply terminal and the respective NW terminal, and wherein the p-n junction is reversely biased.

6. The MV CMOS IC of claim 1 , wherein at least one of the plurality of second CMOS cells is configured to perform a function of a buffer, an inverter, a clock cell, an isolation cell, a tie cell, a power switch header or a level shifter.

7. The MV CMOS IC of claim 1 , wherein a two-dimensional (2D) layout of each of the plurality of second CMOS cells comprise an N-well region extending to two lateral sides of the 2D layout, and wherein each of the two lateral sides of the 2D layout is configured to abut an adjacent second or first CMOS cell of the plurality of second CMOS cells and the plurality of first CMOS cells without an NW-to-NW spacing between the respective second CMOS cell and the adjacent second or first CMOS cell.

8. The MV CMOS IC of claim 1 , further comprising:
a global power grid that comprises a plurality of metal stripes carrying the global supply voltage,
wherein the respective supply terminal of each of the second CMOS cells is electrically coupled to the global supply voltage through the global power grid.

9. The MV CMOS IC of claim 8 , further comprising:
a semiconductor substrate on which the plurality of first CMOS cells and the plurality of second CMOS cells are formed; and
one or more stacked power vias,
wherein, when viewing from a direction substantially perpendicular to a main surface of the semiconductor substrate, the one or more ATAPs are disposed directly under at least one of the plurality of metal stripes of the global power grid, and
wherein the at least one of the plurality of metal stripes of the global power grid is coupled to the one or more ATAPs through the one or more stacked power vias.

10. The MV CMOS IC of claim 8 , wherein the one or more ATAPs are disposed in a linear fashion with respect to the global power grid.

11. The MV CMOS IC of claim 8 , wherein the one or more ATAPs are disposed in a staggered fashion with respect to the global power grid.

Assignees

• Mediatek Singapore Pte Ltd

Inventors

• Jayapal Senthilkumar
• Arumugam Navienkumar Ramachandran

Classifications

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title

• H01L27/0207

  Electricity · mapped topic

• H01L27/0921 Primary

  Electricity · mapped topic

• H01L21/823892

  Electricity · mapped topic

• H01L27/11807

  Electricity · mapped topic