Through plate interconnect for a vertical MIM capacitor

Patent metadata

Field	Value
Publication number	US-12176284-B2
Application number	US-202117398933-A
Country	US
Kind code	B2
Filing date	Aug 10, 2021
Priority date	Apr 2, 2018
Publication date	Dec 24, 2024
Grant date	Dec 24, 2024

Abstract

An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a dielectric layer;
a via, the via comprising a metal extending through the dielectric layer;
an MIM capacitor in the dielectric layer, the MIM capacitor parallel to the via, and the MIM capacitor having an uppermost surface at a same level as an uppermost surface of the dielectric layer; and
a metal plate on the uppermost surface of the dielectric layer, the metal plate in contact with the via and with the MIM capacitor, and the metal plate continuous between the via and the MIM capacitor, wherein the via extends above the metal plate.

2. The integrated circuit structure of claim 1 , further comprising:
a lower dielectric layer, wherein the dielectric layer is above the lower dielectric layer.

3. The integrated circuit structure of claim 2 , further comprising:
an interconnect in the lower dielectric layer.

4. The integrated circuit structure of claim 3 , wherein the via is coupled to the interconnect.

5. The integrated circuit structure of claim 2 , further comprising:
an etch stop layer between the dielectric layer and the lower dielectric layer, wherein the via extends through the etch stop layer.

6. The integrated circuit structure of claim 1 , wherein the MIM capacitor is a vertical MIM capacitor.

7. The integrated circuit structure of claim 1 , wherein MIM capacitor is included in a capacitor over bitline structure.

8. A method of fabricating an integrated circuit structure, the method comprising:
forming a dielectric layer;
forming an MIM capacitor in the dielectric layer, the MIM capacitor having an uppermost surface at a same level as an uppermost surface of the dielectric layer; and
forming a metal plate on the uppermost surface of the dielectric layer and in contact with the MIM capacitor; and
forming a via, the via comprising a metal extending through the dielectric layer, the via in contact with the metal plate, and the via parallel to the MIM capacitor, the metal plate continuous between the via and the MIM capacitor, wherein the via extends above the metal plate.

9. The method of claim 8 , further comprising:
forming a lower dielectric layer, wherein the dielectric layer is formed above the lower dielectric layer.

10. The method of claim 9 , further comprising:
forming an interconnect in the lower dielectric layer.

11. The method of claim 10 , wherein the via is coupled to the interconnect.

12. The method of claim 9 , further comprising:
forming an etch stop layer, the etch stop layer between the dielectric layer and the lower dielectric layer, wherein the via extends through the etch stop layer.

13. The method of claim 8 , wherein the MIM capacitor is a vertical MIM capacitor.

14. The method of claim 8 , wherein MIM capacitor is included in a capacitor over bitline structure.

15. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a dielectric layer;
a via, the via comprising a metal extending through the dielectric layer;
an MIM capacitor in the dielectric layer, the MIM capacitor parallel to the via, and the MIM capacitor having an uppermost surface at a same level as an uppermost surface of the dielectric layer; and
a metal plate on the uppermost surface of the dielectric layer, the metal plate in contact with the via and with the MIM capacitor, and the metal plate continuous between the via and the MIM capacitor, wherein the via extends above the metal plate.

16. The computing device of claim 15 , further comprising:
a memory coupled to the board.

17. The computing device of claim 15 , further comprising:
a battery coupled to the board.

18. The computing device of claim 15 , further comprising:
a communication chip coupled to the board.

19. The computing device of claim 15 , further comprising:
a camera coupled to the board.

20. The computing device of claim 15 , wherein the component is a packaged integrated circuit die.

Assignees

• Intel Corp

Inventors

• Lajoie Travis
• Sharma Abhishek
• Alzate-Vinasco Juan
• Ku Chieh-Jen
• Ogadhoh Shem
• Gardiner Allen
• Lin Blake
• Wang Yih
• Wang Pei-Hua
• Kavalieros Jack T
• Sell Bernhard
• Ghani Tahir

Classifications

• H10W20/48

  Insulating materials thereof · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H10D1/716

  having vertical extensions · CPC title