Deep trench metal-insulator-metal capacitors

Patent metadata

Field	Value
Publication number	US-10083958-B2
Application number	US-201615292488-A
Country	US
Kind code	B2
Filing date	Oct 13, 2016
Priority date	Oct 13, 2016
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

Device structures for a metal-insulator-metal (MIM) capacitor, as well as methods of fabricating a device structure for a MIM capacitor. An active device level is formed on a substrate, a local interconnect level is formed on the active device level, and a metal-insulator-metal capacitor is formed in a via opening with a sidewall extending through the local interconnect level and the active device level to a given depth in the substrate. The metal-insulator-metal capacitor includes a first plate on the sidewall, a second plate, and an interplate dielectric between the first plate and the second plate.

First claim

What is claimed is:

1. A structure comprising:
a substrate;
an active device level on the substrate;
a local interconnect level on the active device level;
a metal-insulator-metal capacitor in a via opening with a sidewall extending through the local interconnect level and the active device level to a given depth in the substrate, the metal-insulator-metal capacitor including a first plate on the sidewall, a second plate, and an interplate dielectric between the first plate and the second plate; and
a resistor in the local interconnect level,
wherein the first plate is coupled with a first portion of the resistor, and the via opening extends through a perforation in the resistor.

2. The structure of claim 1 further comprising:
a first via level on the local interconnect level, the first via level including a contact coupled with a second portion of the resistor.

3. The structure of claim 2 further comprising:
a first metal level on the first via level, the first metal level including a wire coupled by the contact with the second portion of the resistor.

4. The structure of claim 1 wherein the interplate dielectric is hafnium aluminum oxide (HfAlO x ).

5. The structure of claim 1 wherein the interplate dielectric has a dielectric constant that is greater than or equal to 20.

6. The structure of claim 1 wherein the first plate and the second plate are comprised of titanium nitride, and the interplate dielectric is comprised of hafnium aluminum oxide.

7. The structure of claim 1 further comprising:
a first via level on the local interconnect level, the first via level including a first contact coupled with the first plate; and
a first metal level on the first via level, the first metal level including a wire coupled by the first contact with the first plate,
wherein the local interconnect level is located vertically between the substrate and the first metal level.

8. The structure of claim 7 wherein the first via level includes a second contact coupled with the second plate.

9. The structure of claim 8 wherein the first plate and the second plate are comprised of a conductor that is free of copper, and further comprising:
a layer comprised of copper that is positioned in a space interior of the second plate inside the via opening,
wherein the second contact is coupled by the layer with the second plate.

10. The structure of claim 1 wherein the first plate and the second plate are comprised of a conductor that is free of copper.

11. A method comprising:
forming an active device level on a substrate;
forming a local interconnect level on the active device level;
forming a via opening with a sidewall extending through the local interconnect level and the active device level to a given depth in the substrate; and
forming a metal-insulator-metal capacitor that includes a first plate on the sidewall of the via opening, a second plate, and an interplate dielectric between the first plate and the second plate; and
forming a resistor in the local interconnect level, wherein the first plate is coupled with a first portion of the resistor, and the via opening extends through a perforation in the resistor.

12. The method of claim 11 further comprising:
forming a first via level on the local interconnect level,
wherein the first via level includes a contact coupled with a second portion of the resistor.

13. The method of claim 12 further comprising:
forming a first metal level on the first via level,
wherein the first metal level includes a wire coupled by the contact with the second portion of the resistor.

14. The method of claim 11 wherein the interplate dielectric is hafnium aluminum oxide (HfAlO x ).

15. The method of claim 11 further comprising:
forming a first via level on the local interconnect level; and
forming a first metal level on the first via level,
wherein the first via level includes a first contact coupled with the first plate, the first metal level includes a wire coupled with the first contact, and the local interconnect level is located vertically between the substrate and the first metal level.

16. The method of claim 15 further comprising:
forming a second contact in the first via level that is coupled with the second plate.

17. The method of claim 16 wherein the first plate and the second plate are comprised of a conductor that is free of copper, and further comprising:
forming a layer comprised of copper that is positioned in a space interior of the second plate inside the via opening,
wherein the second contact is coupled by the layer with the second plate.

18. The structure of claim 1 wherein the metal-insulator-metal capacitor has a capacitance density greater than 100 nF/mm 2 , and a breakdown voltage greater than 10 volts.

19. The method of claim 11 wherein the metal-insulator-metal capacitor has a capacitance density greater than 100 nF/mm 2 , and a breakdown voltage greater than 10 volts.

Assignees

• Globalfoundries Inc

Inventors

• Kannan Sukeshwar
• Ghosh Somnath
• Smith Daniel
• England Luke

Classifications

• H10W44/241

  for passive devices or passive elements · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W20/498

  Resistive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title