Microelectronic structures having multiple microelectronic devices connected with a microelectronic bridge embedded in a microelectronic substrate

US10418329B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10418329-B2
Application numberUS-201515774937-A
CountryUS
Kind codeB2
Filing dateDec 11, 2015
Priority dateDec 11, 2015
Publication dateSep 17, 2019
Grant dateSep 17, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of forming a microelectronic structure, comprising: forming a first and a second microelectronic device, wherein each of the first and the second microelectronic device include a plurality of high density interconnect structures and a plurality of lower density interconnect structures on an active surface thereof; attaching a microelectronic bridge to the plurality of high density interconnect structures of the first microelectronic device and to the plurality of high density interconnect structures of the second microelectronic device; forming a microelectronic substrate having a cavity defined therein extending from a first surface of the microelectronic substrate, wherein the cavity includes at least one sidewall and a bottom surface; electrically attaching the plurality of lower density interconnect structures of the first microelectronic device and the plurality of lower density interconnect structures of the second microelectronic device to the first surface of the microelectronic substrate, wherein the microelectronic bridge extends into the microelectronic substrate cavity; and disposing an underfill material between the first microelectronic device active surface and the microelectronic substrate first surface, between the second microelectronic device active surface and the microelectronic substrate first surface, and within the microelectronic substrate cavity. 2. The method of claim 1 , wherein the microelectronic bridge electrically connects the first microelectronic device and the second microelectronic device. 3. The method of claim 1 , wherein the microelectronic bridge includes a plurality of conductive routes therein. 4. The method of claim 1 , wherein the microelectronic bridge includes at least one microelectronic device embedded therein. 5. A method of forming a microelectronic structure, comprising: forming a first and a second microelectronic device, wherein each of the first and the second microelectronic device include a plurality of high density interconnect structures and a plurality of lower density interconnect structures on an active surface thereof; forming a reconstituted wafer from the first microelectronic device and the second microelectronic device; attaching a microelectronic bridge to the reconstituted wafer, wherein the microelectronic bridge is attached to the plurality of high density interconnect structures of the first microelectronic device and to the plurality of high density interconnect structures of the second microelectronic device; forming a microelectronic substrate having a cavity defined therein extending from a first surface of the microelectronic substrate, wherein the cavity includes at least one sidewall and a bottom surface; and electrically attaching the plurality of lower density interconnect structures of the first microelectronic device and the plurality of lower density interconnect structures of the second microelectronic device to the first surface of the microelectronic substrate, wherein the microelectronic bridge extends into the microelectronic substrate cavity. 6. The method of claim 5 , wherein forming the reconstituted wafer comprises disposing an encapsulant material between at least one side of the first microelectronic device and at least one side of the second microelectronic device. 7. The method of claim 6 , further including aligning the first microelectronic device and the second microelectronic device on a carrier with the active surface of each of the first microelectronic device and the second device facing the carrier; and wherein disposing the encapsulant material comprises disposing the encapsulant material over a back surface of the first microelectronic device and a back surface of the second microelectronic device. 8. The method of claim 7 , wherein aligning the first microelectronic device and the second microelectronic device on the carrier further comprises adhering the first microelectronic device and the second microelectronic device to the carrier with an adhesive layer. 9. The method of claim 7 , further comprising removing a portion of the encapsulant material to expose the back surface of the first microelectronic device and the back surface of the second microelectronic device. 10. The method of claim 9 , further comprising removing a portion of the in the first microelectronic device and the second microelectronic device. 11. A method forming a microelectronic structure, comprising: forming a first and a second microelectronic device, wherein each of the first and the second microelectronic device include a plurality of high density interconnect structures and a plurality of lower density interconnect structures on an active surface thereof; attaching a microelectronic bridge to the plurality of high density interconnect structures of the first microelectronic device and to the plurality of high density interconnect structures of the second microelectronic device; forming a microelectronic substrate having a cavity defined therein extending from a first surface of the microelectronic substrate, wherein the cavity includes at least one sidewall and a bottom surface; and electrically attaching the plurality of lower density interconnect structures of the first microelectronic device and the plurality of lower density interconnect structures of the second microelectronic device to the first surface of the microelectronic substrate, wherein the microelectronic bridge extends into the microelectronic substrate cavity; wherein attaching the microelectronic bridge to the plurality of high density interconnect structures of the first microelectronic device and to the plurality of high density interconnect structures of the second microelectronic device comprises: aligning a back surface of each of the first microelectronic device and the second microelectronic device on a carrier; disposing a flux material on the plurality of high density interconnect surface of the first microelectronic device and on the plurality of high density interconnect surface of the second microelectronic device; and attaching the microelectronic bridge through the flux material. 12. A microelectronic structure comprising: a first and a second microelectronic device, wherein each of the first and the second microelectronic device includes a plurality of high density interconnect structures and a plurality of lower density interconnect structures on an active surface thereof, a microelectronic bridge attached to the plurality of high density interconnect structures of the first microelectronic device and to the plurality of high density interconnect structures of the second microelectronic device; a microelectronic substrate having a cavity defined therein extending from a first surface of the microelectronic substrate, wherein the cavity includes at least one sidewall and a bottom surface, wherein the plurality of lower density interconnect structures of the first microelectronic device and the plurality of lower density interconnect structures of the second microelectronic device are electrically attached to the first surface of the microelectronic substrate, and wherein the microelectronic bridge extends into the microelectronic substrate cavity; and an underfill material between the first microelectronic device active surface and the microelectronic substrate first surface, between the second microelectronic device active surface and the microelectronic substrate first surface, and within the microelectronic substrate cavity. 13. The microelectronic structure of claim 12 , wherein the microelectronic bridge electrically connects the first mic

Assignees

Inventors

Classifications

  • Materials of bond wires · CPC title

  • the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

  • the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

  • comprising holes having chips therein · CPC title

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What does patent US10418329B2 cover?
A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attache…
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H10W70/68. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 17 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).