Systolic array of arbitrary physical and logical depth

Patent metadata

Field	Value
Publication number	US-12174783-B2
Application number	US-202117304678-A
Country	US
Kind code	B2
Filing date	Jun 24, 2021
Priority date	Jun 24, 2021
Publication date	Dec 24, 2024
Grant date	Dec 24, 2024

Abstract

A processing apparatus includes a processing resource including a general-purpose parallel processing engine and a matrix accelerator. The matrix accelerator includes first circuitry to receive a command to perform operations associated with an instruction, second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction, third circuitry to read operands for the instruction from a register file associated with the systolic array, fourth circuitry to perform operations for the instruction via one or more passes through one or more physical pipeline stages of the systolic array based on a configuration performed by the second circuitry, and fifth circuitry to write output of the operations to the register file associated with the systolic array.

First claim

What is claimed is:

1. A processing apparatus including:
a processing resource including a general-purpose parallel processing engine and a matrix accelerator, the matrix accelerator including:
first circuitry to receive a command to perform operations associated with an instruction;
second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction;
third circuitry to read operands for the instruction from a register file associated with the systolic array;
fourth circuitry to perform operations for the instruction via one or more passes through one or more physical pipeline stages of the systolic array based on a configuration performed by the second circuitry; and
fifth circuitry to write output of the operations to the register file associated with the systolic array.

2. The processing apparatus as in claim 1 , further comprising a tile of graphics processing engines, wherein the tile of graphics processing engines include the processing resource.

3. The processing apparatus as in claim 1 , wherein the instruction is a dot product instruction.

4. The processing apparatus as in claim 1 , wherein to configure the matrix accelerator according to the physical depth of the systolic array and the logical depth associated with the instruction includes to configure the matrix accelerator to perform a partial pass through the systolic array in response to a determination that the physical depth of the systolic array is greater than the logical depth associated with the instruction.

5. The processing apparatus as in claim 4 , wherein to perform the partial pass includes to perform operations for the instruction via less than all physical pipeline stages of the systolic array.

6. The processing apparatus as in claim 5 , wherein the second circuitry is to configure the matrix accelerator to power gate at least one physical pipeline stage of the systolic array during the partial pass.

7. The processing apparatus as in claim 6 , wherein the second circuitry is to configure the matrix accelerator to bypass and power gate one or more upper physical pipeline stages during the partial pass and perform the partial pass via one or more lower physical pipeline stages.

8. The processing apparatus as in claim 1 , wherein to configure the matrix accelerator according to the physical depth of the systolic array and the logical depth associated with the instruction includes to configure the systolic array to perform multiple passes through the systolic array in response to a determination that the logical depth associated with the instruction is greater than the physical depth of the systolic array.

9. The processing apparatus as in claim 8 , wherein to perform the multiple passes includes to perform a first set of operations for the instruction via each of a set of multiple physical pipeline stages of the systolic array and perform a second set of operations for the instruction via at least one physical pipeline stage of the systolic array.

10. The processing apparatus as in claim 1 , wherein the general-purpose parallel processing engine includes circuitry to provide functional units comprising one or more floating-point units and one or more integer units, and the general-purpose parallel processing engine shares access to the register file associated with the systolic array.

11. A method comprising:
receiving a command at a matrix accelerator to perform operations associated with an instruction;
configuring the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction;
reading operands for the instruction from a register file associated with the systolic array;
performing operations for the instruction via one or more passes through one or more stages of the systolic array; and
writing output of the operations to the register file associated with the systolic array.

12. The method as in claim 11 , wherein the instruction is a dot product instruction.

13. The method as in claim 11 , wherein configuring the matrix accelerator according to the physical depth of the systolic array and the logical depth associated with the instruction includes configuring the matrix accelerator to perform a partial pass through the systolic array in response to a determination that the physical depth of the systolic array is greater than the logical depth associated with the instruction and wherein performing the partial pass includes performing operations for the instruction via less than all physical pipeline stages of the systolic array.

14. The method as in claim 11 , further comprising power gating one or more physical pipeline stages of the systolic array during a partial pass.

15. The method as in claim 11 , wherein configuring the matrix accelerator according to the physical depth of the systolic array and the logical depth associated with the instruction includes configuring the systolic array to perform multiple passes through the systolic array in response to a determination that the logical depth associated with the instruction is greater than the physical depth of the systolic array, wherein performing the multiple passes includes performing a first set of operations for the instruction via each of a set of multiple physical pipeline stages of the systolic array and performing a second set of operations for the instruction via at least one physical pipeline stage of the systolic array.

16. A system comprising:
a memory device; and
a graphics processor coupled to the memory device, the graphics processor comprising a processing resource including general-purpose parallel processing engine and a matrix accelerator, the matrix accelerator including:
first circuitry to receive a command to perform operations associated with an instruction;
second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction;
third circuitry to read operands for the instruction from a register file associated with the systolic array;
fourth circuitry to perform operations for the instruction via one or more passes through one or more physical pipeline stages of the systolic array based on a configuration performed by the second circuitry; and
fifth circuitry to write output of the operations to the register file associated with the systolic array.

17. The system as in claim 16 , wherein the instruction is a dot product instruction.

18. The system as in claim 16 , wherein to configure the matrix accelerator according to the physical depth of the systolic array and the logical depth associated with the instruction includes to configure the matrix accelerator to perform a partial pass through the systolic array in response to a determination that the physical depth of the systolic array is greater than the logical depth associated with the instruction, wherein to perform the partial pass includes to perform operations for the instruction via less than all physical pipeline stages of the systolic array and the second circuitry is to configure the matrix accelerator to bypass and power gate one or more upper physical pipeline stages during the partial pass and perform the partial pass via one or more lower physical pipeline stages.

19. The system as in claim 16 , wherein to configure the matrix accelerator according to the physical depth of the systolic arra

Assignees

• Intel Corp

Inventors

• Parra Jorge
• Chen Wei-Yu
• Chen Kaiyu
• George Varghese
• Gu Junjie
• Gurram Chandra
• Lueh Guei-Yuan
• Junkins Stephen
• Maiyuran Subramaniam
• Pal Supratim

Classifications

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30038

  using a mask · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F9/544

  Buffers; Shared memory; Pipes · CPC title

• G06F9/5027

  the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title