Matrix operation apparatus

Patent metadata

Field	Value
Publication number	US-9483442-B2
Application number	US-201414194471-A
Country	US
Kind code	B2
Filing date	Feb 28, 2014
Priority date	Sep 13, 2013
Publication date	Nov 1, 2016
Grant date	Nov 1, 2016

Abstract

According to an embodiment, a matrix operation apparatus executing a matrix operation includes multiple nodes, the nodes including: a multiplier configured to perform a first operation for a first input, which is column data and a second input which is row data for the matrix operation and output element components of an operation result of the matrix operation; and an accumulator configured to perform cumulative addition of operation results of the multiplier.

First claim

What is claimed is:

1. A matrix operation apparatus executing a matrix operation, the apparatus comprising multiple nodes, the nodes each including: a first operation unit configured to perform a first operation for a first input which is column data and a second input which is row data for the matrix operation and output element components of an operation result of the matrix operation; and an accumulator configured to perform cumulative addition of operation results of the first operation unit,
wherein each of the multiple nodes includes: a first input terminal configured to receive the column data of one of two matrices targeted by the matrix operation; a second input terminal configured to receive the row data of the other of the two matrices; a first output terminal configured to output the column data received; and a second output terminal configured to output the row data received.

2. The matrix operation apparatus according to claim 1 , wherein each of the multiple nodes includes a third output terminal configured to output a cumulative addition result of the accumulator.

3. The matrix operation apparatus according to claim 2 , wherein a subsequent-stage node, among the multiple nodes, includes a third input terminal for receiving an operation result of a prior-stage node.

4. The matrix operation apparatus according to claim 3 , wherein
the subsequent node includes a first selection circuit configured to select and output any of an input of the third input terminal and a cumulative addition result of the accumulator; and
the third output terminal outputs the cumulative addition result of the accumulator via the first selection circuit.

5. The matrix operation apparatus according to claim 1 , wherein
a subsequent-stage node, among the multiple nodes, includes a first selection circuit configured to select and output any of an input of the second input terminal and a cumulative addition result of the accumulator; and
the second output terminal outputs the cumulative addition result of the accumulator via the first selection circuit.

6. The matrix operation apparatus according to claim 5 , comprising a control unit configured to control execution of a cumulative addition operation of the accumulator.

7. The matrix operation apparatus according to claim 6 , wherein the control unit controls selection of the first selection circuit.

8. The matrix operation apparatus according to claim 1 , wherein
there are multiple blocks including the multiple nodes;
the multiple blocks include a prior-stage block and a subsequent-stage block; and
in the subsequent-stage block, the row data is inputted to the second input terminals of the multiple nodes via a first selection circuit configured to select and output any of a cumulative addition result of the accumulator of each node included in the prior-stage block and an input from other than the prior-stage block.

9. The matrix operation apparatus according to claim 8 , wherein
the multiple blocks are connected in a matrix shape; and
the cumulative addition result inputted to the first selection circuit is a cumulative addition result of the accumulator of each node included in a prior-stage block on a same row of the matrix.

10. The matrix operation apparatus according to claim 9 , wherein the cumulative addition result inputted to the first selection circuit is a cumulative addition result of the accumulator of each node included in a prior-stage block on a different column of the matrix.

11. The matrix operation apparatus according to claim 8 , comprising:
a second operation unit configured to perform a second operation for the column data and the row data for the matrix operation and outputs of the multiple blocks; and
a second selection circuit configured to select and output any of the outputs of the multiple blocks and an output of the second operation unit.

12. The matrix operation apparatus according to claim 11 , comprising a control unit configured to control execution of a cumulative addition operation of the accumulator and to control selection of the first selection circuit and the second selection circuit.

13. The matrix operation apparatus according to claim 8 , wherein each of the multiple nodes includes a third output terminal configured to output a cumulative addition result of the accumulator.

14. The matrix operation apparatus according to claim 13 , wherein a subsequent-stage node, among the multiple nodes, includes a third input terminal for receiving an operation result of a prior-stage node.

15. The matrix operation apparatus according to claim 14 , wherein
the subsequent node includes a second selection circuit configured to select and output any of an input of the third input terminal and a cumulative addition result of the accumulator; and
the third output terminal outputs the cumulative addition result of the accumulator via the second selection circuit.

16. The matrix operation apparatus according to claim 8 , wherein the first operation unit is a multiplier.

17. The matrix operation apparatus according to claim 8 , comprising a control unit configured to control execution of a cumulative addition operation of the accumulator.

18. The matrix operation apparatus according to claim 1 , wherein the first operation unit is a multiplier.

Assignees

• Toshiba Kk

Inventors

• Maeda Seiji
• Usui Hiroyuki

Classifications

• G06F17/16 Primary

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title