Hybrid resistive memory

Patent metadata

Field	Value
Publication number	US-12170109-B2
Application number	US-202117454311-A
Country	US
Kind code	B2
Filing date	Nov 10, 2021
Priority date	Nov 12, 2020
Publication date	Dec 17, 2024
Grant date	Dec 17, 2024

Abstract

The present disclosure relates to a memory circuit comprising: a transistor layer; a plurality of first memory elements positioned in a first level above the transistor layer; and a plurality of filament switching resistive memory elements positioned in a second level higher than the first level.

First claim

What is claimed is:

1. A memory circuit comprising:
a transistor layer;
a plurality of first memory elements positioned in a first level above the transistor layer;
a plurality of filament switching resistive memory elements positioned in a second level higher than the first level, wherein the first memory elements and the filament switching resistive memory elements are positioned in different levels of a same region of the device;
at least one first interconnection level separating the first and second levels, wherein the at least one first interconnection level is dedicated to the routing of the first memory elements; and
at least one second interconnection level, separating the first and second levels or being higher than the second level, dedicated to the routing of the filament switching resistive memory elements.

2. The memory circuit of claim 1 , wherein the plurality of first memory elements comprises:
one or more phase change memory elements; and/or
one or more ferroelectric tunnel junction memory elements; and/or
one or more oxide random access memory elements.

3. The memory circuit of claim 1 , wherein the plurality of filament switching resistive memory elements comprises one or more conductive bridging memory elements and/or one or more oxide random access memory elements.

4. The memory circuit of claim 1 , wherein the first level is positioned directly on the transistor layer.

5. A method of fabrication of a resistive memory circuit comprising:
forming a transistor layer of the resistive memory circuit;
forming at least one first interconnection level;
forming, in a first region of the circuit, a plurality of first memory elements in a first level above the transistor layer; and
forming, in a second region of the circuit, a plurality of filament switching resistive memory elements in a second level higher than the first level, there being no overlap between the first and second regions, wherein the at least one first interconnection level separates the first and second levels and is configured to provide routing at least between the first memory elements.

6. The method of claim 5 , wherein the plurality of first memory elements comprises:
one or more phase change memory elements; and/or
one or more ferroelectric tunnel junction memory elements; and/or
one or more oxide random access memory elements.

7. The method of claim 5 , wherein the plurality of filament switching resistive memory elements comprises one or more conductive bridging memory elements and/or one or more oxide random access memory elements.

8. The method of claim 5 , wherein the first level is formed directly on the transistor layer.

9. A memory circuit comprising:
a transistor layer;
a plurality of first memory elements positioned in a first level above the transistor layer;
a plurality of filament switching resistive memory elements positioned in a second level higher than the first level;
at least one first interconnection level separating the first and second levels, wherein the at least one first interconnection level is configured to provide routing at least between the first memory elements, wherein the plurality of first memory elements are positioned in a first region of the circuit, and the plurality of filament switching resistive memory elements are positioned in a second region of the circuit, there being no overlap between the first and second regions.

10. The memory circuit of claim 9 , further comprising at least one interconnection level comprising:
in a region aligned with the first region, routing tracks that are dedicated to the first memory elements; and
in a region aligned with the second region, routing tracks that are dedicated to the filament switching memory elements.

11. A method of fabrication of a resistive memory circuit comprising:
forming a transistor layer of the resistive memory circuit;
forming, in a first region of the circuit, a plurality of first memory elements in first level above the transistor layer;
forming at least one first interconnection level;
forming, in the first region of the circuit, a plurality of filament switching resistive memory elements in a second level higher than the first level; and
forming at least one second interconnection level, wherein:
the at least one first interconnection level separates the first and second levels and is dedicated to the routing of the first memory elements; and
the at least one second interconnection level separates the first and second levels or is higher than the second level, and is dedicated to the routing of the filament switching resistive memory elements.

Assignees

• Commissariat A Ienergie Atomique Et Aux Energies Alternatives
• Commissariat Energie Atomique

Inventors

• Vianello Elisa
• Nodin Jean-François

Classifications

• H10N70/231

  based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect · CPC title

• H10N70/021

  Formation of switching materials, e.g. deposition of layers · CPC title

• H10B63/30 Primary

  comprising selection components having three or more electrodes, e.g. transistors · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title

• G11C13/0011

  comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs] · CPC title