Nonvolatile bipolar junction memory cell

Patent metadata

Field	Value
Publication number	US-9711718-B1
Application number	US-201615141761-A
Country	US
Kind code	B1
Filing date	Apr 28, 2016
Priority date	Apr 28, 2016
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

The present disclosure generally relates to an apparatus for a three terminal nonvolatile memory cell. Specifically, a three terminal nonvolatile bipolar junction transistor. The bipolar junction memory device includes a collector layer, a base layer disposed on the collector layer, an emitter layer disposed on the base layer, and a conductive anodic filament extending from the collector layer to the base layer. As current is applied to the transistor and a voltage is applied between P-N junction of the collector layer and the base layer, a conductive anodic filament (CAF) forms. The CAF is non-volatile and short circuits the reverse-biased P-N junction barrier thus keeping the device in a low-resistive state. Removing the CAF switches the device back to a high resistive state. Thus, a new type of semiconductor device advantageously combines computation and memory to form a flux-linkage modulated memory cell.

First claim

What is claimed is:

1. A bipolar junction memory device, comprising:
a collector layer;
a base layer disposed on the collector layer;
an emitter layer disposed on the base layer; and
a conductive anodic filament extending from the collector layer to the base layer.

2. The device of claim 1 , wherein the collector layer is N-conducting.

3. The device of claim 2 , wherein the base layer is P-conducting.

4. The device of claim 3 , wherein the emitter layer is N-conducting.

5. The device of claim 1 , wherein the collector layer is P-conducting.

6. The device of claim 5 , wherein the base layer is N-conducting.

7. The device of claim 6 , wherein the emitter layer is P-conducting.

8. The device of claim 1 , wherein the base layer, collector layer and emitter layer each comprise compounds that include copper.

9. A memory array comprising one or more bipolar junction memory devices, at least one of the devices, comprising:
a collector layer;
a base layer disposed on the collector layer;
an emitter layer disposed on the base layer; and
a conductive anodic filament extending from the collector layer to the base layer.

10. The memory array of claim 9 , wherein the collector layer is N-conducting.

11. The memory array of claim 10 , wherein the base layer is P-conducting.

12. The memory array of claim 11 , wherein the emitter layer is N-conducting.

13. The memory array of claim 12 , wherein the base layer, the collector layer and the emitter layer each comprise compounds that include copper.

14. The memory array of claim 9 , wherein the base layer, the collector layer and the emitter layer each comprise compounds that include copper.

Assignees

• Western Digital Tech Inc

Inventors

• Bedau Daniel

Classifications

• H01L45/1206 Primary

  Electricity · mapped topic

• H01L45/1266

  Electricity · mapped topic

• H01L45/085

  Electricity · mapped topic

• H01L45/1226

  Electricity · mapped topic

• H01L45/146

  Electricity · mapped topic