Nonvolatile memory device including ferroelectric memory element and resistive memory element, and method of operating nonvolatile memory device

Patent metadata

Field	Value
Publication number	US-10497433-B2
Application number	US-201816016548-A
Country	US
Kind code	B2
Filing date	Jun 23, 2018
Priority date	Jul 14, 2017
Publication date	Dec 3, 2019
Grant date	Dec 3, 2019

Abstract

A nonvolatile memory device according to one embodiment includes a ferroelectric memory element and a resistive memory element. The ferroelectric memory element includes a field effect transistor having a ferroelectric gate dielectric layer. The resistive memory element includes a resistance change memory layer disposed between a first memory electrode and a second memory electrode. A drain electrode of the field effect transistor is connected to the first memory electrode or second memory electrodes.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a ferroelectric memory element and a resistive memory element,
wherein the ferroelectric memory element comprises a field effect transistor having a ferroelectric gate dielectric layer,
the resistive memory element comprises a resistance change memory layer disposed between a first memory electrode and a second memory electrode, and
a drain electrode of the field effect transistor is connected to the first memory electrode or the second memory electrode,
wherein the resistance change memory layer includes a conductive filament electrically connecting the first and the second memory electrode,
wherein the conductive filament has a first width in a first state and a second width in a second state, and
wherein the first width is greater than the second width, such that the electron conductivity through the conductive filament varies based on the width.

2. The nonvolatile memory device of claim 1 , wherein the ferroelectric gate dielectric layer has a remanent polarization, and the resistance change memory layer has a resistance, and the remanent polarization and the resistance are independent from each other.

3. The nonvolatile memory device of claim 1 , wherein the ferroelectric gate dielectric layer has one of at least two remanent polarization states.

4. The nonvolatile memory device of claim 3 , wherein the ferroelectric memory element has a channel resistance state corresponding to the stored remanent polarization state.

5. The nonvolatile memory device of claim 1 , wherein the resistance change memory layer has one of at least two resistance states.

6. The nonvolatile memory device of claim 1 , wherein the field effect transistor comprises:
a semiconductor substrate;
a crystalline ferroelectric material layer disposed on the semiconductor substrate;
a gate electrode layer disposed on the ferroelectric material layer;
a drain electrode and a source electrode disposed in the semiconductor substrate at opposite ends of the gate electrode layer.

7. The nonvolatile memory device of claim 6 , wherein the resistive memory element comprises the first memory electrode, the resistance change memory layer and the second memory electrode sequentially disposed on the semiconductor substrate,
and wherein the first memory electrode is connected to the drain electrode.

8. The nonvolatile memory device of claim 6 , wherein the semiconductor substrate comprises one of silicon (Si), gallium arsenide (GaAs), indium phosphide (InP), germanium (Ge), and silicon germanium (SiGe).

9. The nonvolatile memory device of claim 6 , wherein the semiconductor substrate is doped with an n-type dopant or a p-type dopant.

10. The nonvolatile memory device of claim 1 , wherein the ferroelectric gate dielectric layer comprises at least one selected from the group consisting of hafnium oxide (HfO2), zirconium oxide (ZrO2), lead zirconium titanium oxide (PbZr0.5Ti0.5O3), barium titanium oxide (BaTiO3), lead titanium oxide (PbTiO3), hafnium zirconium oxide (Hf0.5Zr0.5O2), lithium niobium oxide (LiNbO3), lithium tantalum oxide (LiTaO3), strontium bismuth tantalum oxide (SrBi2Ta2O9), (bismuth, lanthanum) titanium oxide ((Bi, La)4Ti3O12)), and bismuth titanium oxide (Bi4Ti3O12).

11. The nonvolatile memory device of claim 10 , wherein the ferroelectric gate dielectric layer comprises a dopant, and
the dopant comprises at least one selected from the group consisting of carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd), and lanthanum (La).

12. The nonvolatile memory device of claim 1 , wherein the resistance change memory layer comprises at least one selected from the group consisting of titanium oxide, aluminum oxide, nickel oxide, copper oxide, zirconium oxide, manganese oxide, hafnium oxide, tungsten oxide, tantalum oxide, niobium oxide, iron oxide, PCMO (Pr1-xCaxMnO3, 0<x<1), LCMO (La1-xCaxMnO3, 0<x<1), BSCFO (Ba0.5Sr0.5Co0.8Fe0.2O3-δ), YBCO (YBa2Cu3O7-x, 0<x<1), (Ba, Sr)TiO3(Cr-doped, Nb-doped), SrZrO3(Cr-doped, V-doped), (La, Sr)MnO3, Sr1-xLaxTiO3 (0<x<1), La1-xSrxFeO3 (0<x<1), La1-xSrxCoO3 (0<x<1), SrFeO2.7, LaCoO3, RuSr2GdCu2O3, YBa2Cu3O7, germanium-antimony-tellurium (Ge—Sb—Te; GST), arsenic-antimony-tellurium (As—Sb—Te), tin-antimony-tellurium (Sn—Sb—Te), tin-indium-antimony-tellurium (Sn—In—Sb—Te), arsenic-germanium-antimony-tellurium (As—Ge—Sb—Te), GexSel-x (0<x<1), silver sulfide (Ag2S), copper sulfide (Cu2S), cadmium sulfide (CdS), zinc sulfide (ZnS), and selenium oxide (CeO2).

Assignees

• Sk Hynix Inc

Inventors

• Lee Sanghun

Classifications

• G11C11/5657 Primary

  using ferroelectric storage elements · CPC title

• G11C13/0007

  comprising metal oxide memory material, e.g. perovskites · CPC title

• G11C2213/31

  Material having complex metal oxide, e.g. perovskite structure · CPC title

• G11C11/5678

  using amorphous/crystalline phase transition storage elements · CPC title

• G11C11/2275

  Writing or programming circuits or methods · CPC title