Caching for multiple-level memory device

Patent metadata

Field	Value
Publication number	US-12169648-B2
Application number	US-202217888325-A
Country	US
Kind code	B2
Filing date	Aug 15, 2022
Priority date	Aug 15, 2022
Publication date	Dec 17, 2024
Grant date	Dec 17, 2024

Abstract

Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.

First claim

What is claimed is:

1. A memory system, comprising:
one or more memory devices comprising a plurality of memory cells; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
receive first data to be written to the one or more memory devices;
write, based at least in part on receiving the first data to be written to the one or more memory devices, the first data to a first set of cells of the plurality of memory cells using a first programming mode, the first programming mode being a single-level programming mode;
transfer, based at least in part on writing the first data to the first set of cells, the first data from the first set of cells to a second set of cells of the plurality of memory cells using a second programming mode, the second programming mode being a quad-level programming mode;
receive, after receiving the first data, second data to be written to the one or more memory devices; and
determine whether to write the second data to a third set of cells of the plurality of memory cells using the first programming mode or a third programming mode based at least in part on available cells of the plurality of memory cells that are ready for programming, wherein:
the plurality of memory cells are programmable using a fourth programming mode, and
the third programming mode and the fourth programming mode are tri-level programming modes, the third programming mode being associated with a first order for programming a lower page and one or more upper pages, and the fourth programming mode being associated with a second, different, order for programming the lower page and the one or more upper pages.

2. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
write, based at least in part on determining to use the third programming mode, the second data to the third set of cells using the third programming mode.

3. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
determine, based at least in part on receiving the second data, a logical saturation of the one or more memory devices, wherein a quantity of the available cells is based at least in part on the logical saturation; and
compare the logical saturation with a threshold logical saturation.

4. The memory system of claim 1 , wherein, as part of determining whether to use the first programming mode or the third programming mode, the processing circuitry is further configured to cause the memory system to:
determine to use the third programming mode based at least in part on a logical saturation of the one or more memory devices satisfying a threshold logical saturation.

5. The memory system of claim 4 , wherein the logical saturation of the one or more memory devices is based at least in part on a quantity of logical addresses of the one or more memory devices that are used relative to a quantity of logical addresses supported by the one or more memory devices.

6. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
determine, based at least in part on receiving the second data, a quantity of the available cells; and
compare the quantity of the available cells with a threshold quantity.

7. The memory system of claim 1 , wherein, as part of determining whether to use the first programming mode or the third programming mode, the processing circuitry is further configured to cause the memory system to:
determine to use the third programming mode based at least in part on a quantity of the available cells being less than a threshold quantity.

8. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
perform a garbage collection operation while the second data is written to the third set of cells to make available a fourth set of cells for storing the second data.

9. The memory system of claim 1 , wherein, as part of determining whether to use the first programming mode or the third programming mode, the processing circuitry is further configured to cause the memory system to:
determine to use the third programming mode based at least in part on a rate at which unavailable cells are made available being less than a rate at which available cells are written to using the first programming mode.

10. The memory system of claim 1 , wherein
the processing circuitry is further configured to cause the memory system to:
write, based at least in part on determining to use the third programming mode, the second data to the third set of cells using the third programming mode in accordance with the first order.

11. The memory system of claim 10 , wherein the processing circuitry is further configured to cause the memory system to:
transmit a command directing the one or more memory devices to use the third programming mode based at least in part on determining to use the third programming mode.

12. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
write the second data to the third set of cells using the third programming mode based at least in part on determining to use the third programming mode; and
transfer, using the second programming mode, the second data to a fourth set of cells of the plurality of memory cells.

13. The memory system of claim 12 , wherein, to transfer the second data to the fourth set of cells, the processing circuitry is further configured to cause the memory system to:
perform a first operation for reading first pages of the third set of cells to obtain a first portion of the second data; and
perform a second operation for reading second pages and third pages of the third set of cells to obtain a remaining portion of the second data.

14. A memory system, comprising:
one or more memory devices comprising a plurality of memory cells; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
receive first data to be written to the one or more memory devices;
write, based at least in part on receiving the first data to be written to the one or more memory devices, the first data to a first set of cells of the plurality of memory cells using a first programming mode, the first programming mode being a single-level programming mode;
transfer, based at least in part on writing the first data to the first set of cells, the first data from the first set of cells to a second set of cells of the plurality of memory cells using a second programming mode, the second programming mode being a quad-level programming mode;
receive, after receiving the first data, second data to be written to the one or more memory devices; and
determine whether to write the second data to a third set of cells of the plurality of memory cells using the first programming mode or a third programming mode based at least in part on available cells of the plurality of memory cells that are ready for programming, the third programming mode being a tri-level programming mode,
wherein, based at least in part on determining to use the third programming mode, the processing circuitry is further configured to cause the memory system to:
program, in a first round of programming, first pages of the third set of cells using the first programming mode; and
program, in a second round of programming, second pages, third pages, or both, of the third set of cells.

15. A non-transitory, computer-readable medium storing code c

Assignees

• Micron Technology Inc

Inventors

• Basu Reshmi
• Parry Jonathan S
• Gohain Nitul

Classifications

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F12/0253

  Garbage collection, i.e. reclamation of unreferenced memory · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title