SLC cache management

Patent metadata

Field	Value
Publication number	US-10545685-B2
Application number	US-201715690869-A
Country	US
Kind code	B2
Filing date	Aug 30, 2017
Priority date	Aug 30, 2017
Publication date	Jan 28, 2020
Grant date	Jan 28, 2020

Abstract

Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.

First claim

The invention claimed is:

1. A memory device, the memory device comprising:
an array of memory cells, the memory cells in the array configurable as either a multi-level cell (MLC) configuration or a single level cell (SLC) configuration;
a controller, the controller executing firmware instructions, which cause the controller to perform operations comprising:
receiving, from a host device, over a communications interface, a behavior profile for an SLC cache of the memory device, the behavior profile describing at least one of: one or more rules for determining, based upon a performance metric of the memory device, a size of the SLC cache or one or more rules for reconfiguring the SLC cache;
configuring memory cells of the array as belonging either to an SLC cache pool or an MLC storage pool based upon the behavior profile;
receiving a write command to write data to the memory device;
writing the data to the SLC cache pool; and
subsequent to writing the data to the SLC cache pool, transferring the data to the MLC storage pool;
subsequent to transferring the data to the MLC storage pool, receiving, from the host device, over the communications interface, an updated behavior profile for the SLC cache of the memory device, and
responsive to receiving the updated behavior profile, reconfiguring the memory cells of the array as belonging to an SLC cache pool or an MLC storage pool according to the updated behavior profile.

2. The memory device of claim 1 , wherein the communications interface is a Universal Flash Storage interface.

3. The memory device of claim 1 , wherein the behavior profile comprises a target logical block addressing (LBA) saturation threshold and a corresponding target size of the SLC cache, and wherein the operations further comprise:
determining that a current LBA saturation exceeds the target LBA saturation threshold, and in response, adjusting the configuration of the memory cells in the array such that a number of the memory cells in the SLC cache produces an SLC cache size that is the target size.

4. The memory device of claim 1 , wherein the write command is received from a host over an interface implemented according to a Universal Flash Storage (UFS) standard.

5. The memory device of claim 1 , wherein the operations of receiving the behavior profile of the SLC cache of the memory device and configuring memory cells of the array as belonging either to the SLC cache pool or the MLC storage pool based upon the behavior profile are performed upon a first execution of a firmware object containing the firmware instructions.

6. The memory device of claim 1 , wherein the behavior profile comprises a target activity threshold and a corresponding target size of the SLC cache, and wherein the operations further comprise:
determining that a current activity threshold exceeds the target activity threshold, and in response, adjusting the configuration of the memory cells in the array such that a number of the memory cells in the SLC cache produces an SLC cache size that is the target size.

7. The memory device of claim 1 , wherein the behavior profile includes a write activity threshold and wherein the operations further comprise:
receiving a second write command to write second data to the memory device; and
determining that write activity of the memory device is below the write activity threshold, and in response, writing the second data to the MLC storage pool, bypassing the SLC cache.

8. The memory device of claim 7 , wherein the write activity threshold is a number of pending write requests.

9. A method comprising:
at a memory device comprising an array of memory cells, the memory cells in the array configurable as either a multi-level cell (MLC) configuration or a single level cell (SLC) configuration, using a controller, performing operations comprising:
receiving, from a host device, over a communications interface, a behavior profile for an SLC cache of the memory device, the behavior profile describing at least one of: rules for determining, based upon a performance metric of the memory device, a size of the SLC cache or one or more rules for reconfiguring the SLC cache;
configuring memory cells of the array as belonging either to an SLC cache pool or an MLC storage pool based upon the behavior profile;
receiving a write command to write data to the memory device;
writing the data to the SLC cache pool; and
subsequent to writing the data to the SLC cache pool, transferring the data to the MLC storage pool;
subsequent to transferring the data to the MLC storage pool, receiving, from the host device, over the communications interface, an updated behavior profile for the SLC cache of the memory device; and
responsive to receiving the updated behavior profile, reconfiguring the memory cells of the array as belonging to an SLC cache pool or an MLC storage pool according to the updated behavior profile.

10. The method of claim 9 , wherein the communications interface is a Universal Flash Storage interface.

11. The method of claim 9 , wherein the behavior profile comprises a target logical block addressing (LBA) saturation threshold and a corresponding target size of the SLC cache, and wherein the operations further comprise:
determining that a current LBA saturation exceeds the target LBA saturation threshold, and in response, adjusting the configuration of the memory cells in the array such that a number of the memory cells in the SLC cache produces an SLC cache size that is the target size.

12. The method of claim 9 , wherein the write command is received from a host over an interface implemented according to a Universal Flash Storage (UFS) standard.

13. The method of claim 9 , wherein the operations of receiving the behavior profile of the SLC cache of the memory device and configuring memory cells of the array as belonging either to the SLC cache pool or the MLC storage pool based upon the behavior profile are performed upon a first execution of a firmware object containing the firmware instructions.

14. The method of claim 9 , wherein the behavior profile comprises a target activity threshold and a corresponding target size of the SLC cache, and wherein the operations further comprise:
determining that a current activity threshold exceeds the target activity threshold, and in response, adjusting the configuration of the memory cells in the array such that a number of the memory cells in the SLC cache produces an SLC cache size that is the target size.

15. The method of claim 9 , wherein the behavior profile includes a write activity threshold and wherein the operations further comprise:
receiving a second write command to write second data to the memory device; and
determining that write activity of the memory device is below the write activity threshold, and in response, writing the second data to the MLC storage pool, bypassing the SLC cache.

16. The method of claim 15 , wherein the write activity threshold is a number of pending write requests.

17. A machine-readable medium comprising instructions, that when executed by a machine, cause the machine to perform operations comprising:
receiving, from a host device, over a communications interface, a behavior profile for an SLC cache of a memory device, the behavior profile describing at least one of: rules for determining, based upon a performance metric of the memory device, a size of the SLC cache or one or more rules for reconfiguring the SLC cache;
configuring memory cells of an array of memory cells as belonging either to an SLC cache pool or an MLC storage pool based upon

Assignees

• Micron Technology Inc

Inventors

• Tanpairoj Kulachet
• Jean Sebastien Andre
• Muchherla Kishore Kumar
• Malshe Ashutosh
• Huang Jianmin

Classifications

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title

• G06F2212/7202

  Allocation control and policies · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/283

  Plural cache memories · CPC title

• G06F3/0655

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title