Semiconductor package, and a package on package type semiconductor package having the same

Patent metadata

Field	Value
Publication number	US-12166013-B2
Application number	US-202217578621-A
Country	US
Kind code	B2
Filing date	Jan 19, 2022
Priority date	May 6, 2021
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

A semiconductor package including: a redistribution layer including redistribution line patterns, redistribution vias connected to the redistribution line patterns, and a redistribution insulating layer surrounding the redistribution line patterns and the redistribution vias; semiconductor chips including at least one upper semiconductor chip disposed on a lowermost semiconductor chip of the semiconductor chips, wherein the at least one upper semiconductor chip is thicker than the lowermost semiconductor chip; bonding wires each having a first end and a second end, wherein the bonding wires connect the semiconductor chips to the redistribution layer, wherein the first end of each of the bonding wires is connected to a respective chip pad of the semiconductor chips and the second end of each of the bonding wires is connected to a respective one of the redistribution line patterns; and a molding member surrounding, on the redistribution layer, the semiconductor chips and the bonding wires.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a redistribution layer comprising a plurality of redistribution lines, a plurality of redistribution vias connected to some of the plurality of redistribution lines, and a redistribution insulating layer surrounding some of the plurality of redistribution lines and the plurality of redistribution vias;
a plurality of semiconductor chips comprising at least one upper semiconductor chip disposed on a lowermost semiconductor chip of the semiconductor chips, wherein the at least one upper semiconductor chip has a thickness that is greater than a thickness of the lowermost semiconductor chip;
a plurality of bonding wires each having a first end and a second end, wherein the plurality of bonding wires connect the plurality of semiconductor chips to the redistribution layer, wherein the first end of each of the plurality of bonding wires is connected to a respective chip pad of the plurality of semiconductor chips and the second end of each of the plurality of bonding wires is connected to a respective one of the plurality of redistribution lines; and
a molding member surrounding, on the redistribution layer, the plurality of semiconductor chips and the plurality of bonding wires.

2. The semiconductor package of claim 1 , wherein a lower surface of the lowermost semiconductor chip directly contacts an upper surface of the redistribution layer.

3. The semiconductor package of claim 2 , wherein the at least one upper semiconductor chip comprises a die bonding film attached to a lower surface of the at least one upper semiconductor chip and is stacked on the lowermost semiconductor chip.

4. The semiconductor package of claim 1 , wherein cross-sections of second ends of the plurality of bonding wires connected to the plurality of redistribution lines, a lower surface of the molding member, and a lower surface of the lowermost semiconductor chip form a coplanar surface.

5. The semiconductor package of claim 1 , wherein an inactive surface of each of the plurality of semiconductor chips faces the redistribution layer.

6. The semiconductor package of claim 1 , wherein edges of each of the plurality of semiconductor chips are aligned in a vertical direction.

7. The semiconductor package of claim 1 , wherein the plurality of semiconductor chips are stacked to form a stepwise shape.

8. The semiconductor package of claim 1 , wherein cross-sections of the second ends of the plurality of bonding wires connected to the plurality of redistribution lines each have a circular shape.

9. The semiconductor package of claim 8 , wherein each of the plurality of bonding wires has a ball bond on its first end and is attached to a corresponding chip pad of the plurality of semiconductor chips, and
each of the plurality of bonding wires has a first diameter near a central portion and a second diameter near the ball bonds to which it is connected.

10. A semiconductor package, comprising:
a package board;
a sub-semiconductor package and a second semiconductor chip that are disposed on the package board and separated from each other in a horizontal direction, wherein the sub-semiconductor package comprises a plurality of first semiconductor chips and a first molding member surrounding the plurality of first semiconductor chips; and
a second molding member surrounding, on the package board, the sub-semiconductor package and the second semiconductor chip,
wherein the sub-semiconductor package further comprises:
a redistribution layer comprising a plurality of redistribution lines comprising a redistribution upper pad and a redistribution lower pad, and a redistribution insulating layer surrounding at least a portion of the plurality of redistribution lines;
the plurality of first semiconductor chips comprising a lowermost semiconductor chip that has a lower surface directly contacting an upper surface of the redistribution layer, and at least one upper semiconductor chip stacked on the lowermost semiconductor chip;
a plurality of bonding wires connecting a chip pad of the plurality of first semiconductor chips to the redistribution upper pad; and
the first molding member surrounding, on the redistribution layer, the plurality of first semiconductor chips and the plurality of bonding wires and contacting the second molding member.

11. The semiconductor package of claim 10 , wherein each of the sub-semiconductor package and the second semiconductor chip are attached to the package board according to a flip chip bonding method.

12. The semiconductor package of claim 10 , wherein an inactive surface of each of the plurality of first semiconductor chips faces the redistribution layer.

13. The semiconductor package of claim 10 , wherein the at least one upper semiconductor chip has a die bonding film attached to a lower surface of the at least one upper semiconductor chip and is stacked on the lowermost semiconductor chip.

14. The semiconductor package of claim 10 , wherein the at least one upper semiconductor chip has a first thickness, and the lowermost semiconductor chip has a second thickness that is less than the first thickness.

15. The semiconductor package of claim 10 , wherein a side surface of the redistribution layer is aligned with a side surface of the first molding member in a vertical direction.

16. The semiconductor package of claim 10 , wherein each of the plurality of first semiconductor chips comprises a dynamic random access memory (DRAM) chip, the second semiconductor chip comprises a central processing unit chip, a graphics processing unit chip, or an application processor chip.

17. The semiconductor package of claim 10 , wherein a cross-section of each of the plurality of bonding wires contacting the redistribution upper pad and having a circular shape, a lower surface of the first molding member, and a lower surface of the lower semiconductor chip form a coplanar surface.

18. A package-on-package (PoP) semiconductor package, comprising:
a lower package comprising: a lower package board; a sub-semiconductor package and a second semiconductor chip that are separated from each other on the package board in a horizontal direction, are attached to the lower package board according to a flip chip bonding method, wherein the sub-semiconductor package comprises a plurality of first semiconductor chips and a first molding member surrounding the plurality of first semiconductor chips; a second molding member surrounding the sub-semiconductor package and the second semiconductor chip on the package board; and a through via having a lower surface connected to the lower package board by penetrating the second molding member; and
an upper package comprising: an upper package board attached to the lower package and connected to an upper surface of the through via; and at least one upper chip attached to the upper package board,
wherein the sub-semiconductor package further comprises: a redistribution layer comprising a plurality of redistribution lines comprising a redistribution upper pad and a redistribution lower pad, and a redistribution insulating layer surrounding a portion of the plurality of redistribution lines; the first semiconductor chips comprising a chip pad on an active surface; a plurality of bonding wires connecting the chip pad of the plurality of first semiconductor chips to the redistribution upper pad; and the first molding member surrounding the plurality of first semiconductor chips and the plurality of bonding wires on the redistribution layer, and
a cross-section of the plurality of bonding wires conta

Assignees

• Samsung Electronics Co Ltd

Inventors

• Chung Hyunsoo
• Kim Younglyong
• Chung Myungkee

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title