Semiconductor package including multiple semiconductor chips and method of manufacturing the semiconductor package

Patent metadata

Field	Value
Publication number	US-10784244-B2
Application number	US-201816177968-A
Country	US
Kind code	B2
Filing date	Nov 1, 2018
Priority date	Feb 20, 2018
Publication date	Sep 22, 2020
Grant date	Sep 22, 2020

Abstract

A semiconductor package includes a package substrate, at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate, at least one second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate, at least one third semiconductor chip stacked on the first and second semiconductor chips, and at least one support structure between the at least one second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a package substrate;
at least one first semiconductor chip on the package substrate and having a first height as measured from the package substrate;
a second semiconductor chip on the package substrate spaced apart from the first semiconductor chip and having a second height less than the first height as measured from the package substrate;
at least one third semiconductor chip stacked on the at least one first semiconductor chip and the second semiconductor chip; and
at least one support structure between the second semiconductor chip and the at least one third semiconductor chip configured to support the at least one third semiconductor chip,
wherein the at least one support structure comprises:
at least one dummy pad on the second semiconductor chip; and
at least one dummy wire having first and second end portions adhered to the at least one dummy pad and making contact with a lower surface of the at least one third semiconductor chip.

2. The semiconductor package of claim 1 , wherein the second semiconductor chip comprises a redistribution wiring layer, which is an uppermost layer of the second semiconductor chip, and the redistribution wiring layer comprises the at least one dummy pad.

3. The semiconductor package of claim 2 , wherein the redistribution wiring layer further comprises a plurality of bonding pads connected to a bonding wire.

4. The semiconductor package of claim 1 , further comprising bonding wires electrically connecting the at least one first semiconductor chip and the second semiconductor chip to the package substrate.

5. The semiconductor package of claim 1 , wherein the first height is approximately equal to a sum of a height of the at least one support structure and the second height.

6. The semiconductor package of claim 1 , wherein a thickness of the at least one first semiconductor chip is less than a thickness of the second semiconductor chip.

7. The semiconductor package of claim 1 , wherein the at least one first semiconductor chip comprises a memory chip and the second semiconductor chip comprises a logic chip.

8. A semiconductor package, comprising:
a package substrate;
a plurality of first semiconductor chips stacked sequentially on the package substrate and having a first height as measured from the package substrate;
a second semiconductor chip on the package substrate and having a second height less than the first height as measured from the package substrate;
a plurality of third semiconductor chips stacked on the package substrate so as to at least partially cover the first and second semiconductor chips in a plan view of the semiconductor package; and
at least one support structure between the second semiconductor chip and a lowermost third semiconductor chip of the plurality of third semiconductor chips configured to support the plurality of third semiconductor chips,
wherein the at least one support structure comprises:
at least two dummy pads on the second semiconductor chip; and
at least one dummy wire having first and second end portions adhered to the at least two dummy pads, respectively, and configured to support the lowermost third semiconductor chip.

9. The semiconductor package of claim 8 , wherein the second semiconductor chip comprises a redistribution wiring layer, which is an uppermost layer of the second semiconductor chip, and the redistribution wiring layer comprises the at least two dummy pads.

10. The semiconductor package of claim 8 , further comprising bonding wires electrically connecting the plurality of first semiconductor chips and the second semiconductor chip to the package substrate.

11. A method of manufacturing a semiconductor package, comprising:
sequentially stacking a plurality of first semiconductor chips on the package substrate so as to have a first height as measured from the package substrate;
forming a second semiconductor chip on the package substrate so as to have a second height less than the first height as measured from the package substrate;
forming a support structure on the second semiconductor chip; and
stacking a plurality of third semiconductor chips on the support structure so as to cover the plurality of first semiconductor chips and the second semiconductor chip in a plan view of the semiconductor package,
wherein forming the support structure on the second semiconductor chip comprises forming at least one dummy wire, first and second end portions of the dummy wire being adhered to at least two dummy pads on the second semiconductor chip, respectively.

12. The method of claim 11 , wherein the second semiconductor chip comprises a redistribution wiring layer, which is an uppermost layer of the second semiconductor chip, and the redistribution wiring layer comprises the at least two dummy pads.

13. The method of claim 11 , further comprising electrically connecting the plurality of first semiconductor chips and the second semiconductor chip to the package substrate using bonding wires.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Won-Gil
• Lee Seung-Lo
• Lee Yong-Je
• Cho Sung-Il

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/24

  at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape · CPC title

• H10W90/231

  the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title