Capacitive pressure sensor device including lower and upper electrodes

Patent metadata

Field	Value
Publication number	US-12163854-B2
Application number	US-202217668136-A
Country	US
Kind code	B2
Filing date	Feb 9, 2022
Priority date	Feb 10, 2021
Publication date	Dec 10, 2024
Grant date	Dec 10, 2024

Abstract

A capacitive sensor device is fabricated on a dielectric substrate. The capacitive sensor device may include multiple diaphragms that differ in shape and/or size. Each of the diaphragms is paired to upper and lower electrodes in included upper and lower electrode layers, respectively. The lower layer is on the dielectric substrate and couples the lower electrodes to a lower electrode terminal in parallel. The upper electrode layer is separated from the lower electrode layer by a gap defined by a removed sacrificial layer and couples the upper electrodes in parallel to an upper electrode terminal.

First claim

What is claimed is:

1. A capacitive device including:
a dielectric substrate;
a lower electrode terminal;
a lower electrode layer patterned on top of the dielectric substrate, the lower electrode layer including a first lower electrode and a second lower electrode, the first and second lower electrodes coupled in parallel to the lower electrode terminal, the lower electrode layer, the lower electrode terminal or both in physical contact with the dielectric substrate;
an upper electrode terminal;
an upper electrode layer above the lower electrode layer, the upper electrode layer including a first upper electrode and a second upper electrode, the first and second upper electrodes coupled in parallel to the upper electrode terminal, the upper electrode terminal, the upper electrode layer, or both in physical contact with the dielectric substrate;
a first diaphragm paired to the first lower electrode and the first upper electrode, at least a first portion of a sacrificial layer selectively removed from below the first diaphragm; and
a second diaphragm paired to the second lower electrode and the second upper electrode, the second diaphragm having a difference in size, shape, or both from the first diaphragm.

2. The capacitive device of claim 1 , where the device includes a pressure sensor.

3. The capacitive device of claim 1 , where the sacrificial layer is less than 1 micron thick.

4. The capacitive device of claim 1 , where the difference between the first and second diaphragms is determined to modify a response of the device over a range of pressures.

5. The capacitive device of claim 1 , where the device further includes a heterogenous array of diaphragms including the first and second diaphragms to change the capacitance response of the capacitive device relative to that produced by the first and second diaphragms.

6. The capacitive device of claim 5 , where the full-scale range of the heterogenous array is greater than 10 megapascals.

7. The capacitive device of claim 1 , where the first diaphragm includes a distribution of etchant apertures to allow etchant to permeate through the first diaphragm during removal of the sacrificial layer.

8. The capacitive device of claim 1 , where the second upper electrode includes one or more deformation apertures to mitigate deformation of the second diaphragm caused by temperature-induced effects on the second upper electrode.

9. The capacitive device of claim 1 , where the device further includes a diaphragm layer including:
a first sub-layer including first and second diaphragms; and
a second reinforcement sub-layer.

10. The capacitive device of claim 1 , where:
the removed sacrificial layer includes a tapered sidewall; and
the device further includes a diaphragm layer in which the first and second diaphragms are patterned, the diaphragm layer including a sloped sidewall due the tapered sidewall prior to removal of the sacrificial layer.

11. A method of manufacture including;
patterning, using a dielectric substrate process, a lower electrode layer on a dielectric substrate, the lower electrode layer including multiple lower electrodes coupled in parallel;
patterning a sacrificial layer above the lower electrode layer;
after patterning the sacrificial layer:
patterning an upper electrode layer above the sacrificial layer, the upper electrode layer including multiple upper electrodes, each of the multiple upper electrodes paired to a respective one of the multiple lower electrodes; and

patterning a diaphragm layer above the sacrificial layer; and
after patterning the diaphragm layer:

removing at least of portion of the sacrificial layer from below one or more diaphragms in the diaphragm layer.

12. The method of manufacture of claim 11 , where the dielectric substrate includes a homogenous dielectric substrate at least 50 microns thick.

13. The method of manufacture of claim 11 , where patterning the sacrificial layer includes patterning a layer that is less than 1 micron thick.

14. The method of manufacture of claim 11 , where:
patterning the sacrificial layer includes patterning a layer with a tapered sidewall; and
patterning the diaphragm layer includes patterning the diaphragm layer with a sloped sidewall due to the tapered sidewall of the sacrificial layer.

15. The method of manufacture of claim 11 , where removing at least of portion of the sacrificial layer includes etching the sacrificial layer by permeating etchant through one or more etchant apertures patterned into the one or more diaphragms.

16. The method of manufacture of claim 11 , where patterning the upper electrode layer includes patterning an upper electrode the upper electrode layer paired with a diaphragm in the diaphragm layer, the upper electrode including one or more deformation apertures to allow of temperature-induced deformation of the upper electrode without damage the diaphragm paired to the upper electrode.

17. The method of manufacture of claim 11 , where patterning the diaphragm layer includes:
patterning a first diaphragm; and
patterning a second diaphragm that differs from the first diaphragm in size, shape, or both.

18. The method of manufacture of claim 17 , where:
patterning the lower electrode layer includes patterning first and second lower electrodes respectively paired to the first and second diaphragms, the first and second lower electrodes coupled in parallel to a lower electrode terminal; and
patterning the upper electrode layer includes patterning first and second upper electrodes respectively paired to the first and second diaphragms, the first and second upper electrodes coupled in parallel to an upper electrode terminal different than the lower electrode terminal.

19. A capacitive pressure sensor device including:
a dielectric substrate;
a lower electrode terminal;
a lower electrode layer on the dielectric substrate, the lower electrode layer including multiple lower sensor electrodes coupled in parallel to the lower electrode terminal;
a sacrificial layer gap;
an upper electrode terminal in physical contact with the dielectric substrate;
an upper electrode layer separated from the lower electrode layer by the sacrificial layer gap, the upper electrode layer including multiple upper sensor electrodes each paired to a respective lower sensor electrode and coupled in parallel to the upper electrode terminal; and
a diaphragm layer disposed above the upper electrode layer.

20. The capacitive pressure sensor device of claim 19 , where the diaphragm layer includes at least two diaphragms that differ in size, shape, or both, the at least two diaphragms each disposed above a respective upper sensor electrode.

Assignees

• Univ Michigan Regents

Inventors

• Benken Alexander
• Gianchandani Yogesh

Classifications

• G01L9/0042 Primary

  Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms (details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively) · CPC title

• G01L9/0073 Primary

  using a semiconductive diaphragm · CPC title