Capacitive pressure with Ti electrode

Patent metadata

Field	Value
Publication number	US-11585711-B2
Application number	US-201916958269-A
Country	US
Kind code	B2
Filing date	Jan 10, 2019
Priority date	Jan 10, 2018
Publication date	Feb 21, 2023
Grant date	Feb 21, 2023

Abstract

A capacitive sensor is disclosed. In an embodiment a semiconductor device includes a die including a capacitive pressure sensor integrated on a CMOS circuit, wherein the capacitive pressure sensor includes a first electrode and a second electrode separated from one another by a cavity, the second electrode including a suspended tensile membrane, and wherein the first electrode is composed of one or more aluminum-free layers containing Ti.

First claim

What is claimed is:

1. A semiconductor device comprising:
a die including a capacitive pressure sensor integrated on a CMOS circuit,
wherein the capacitive pressure sensor includes a first electrode and a second electrode separated from one another by a cavity, the second electrode including a suspended tensile membrane,
wherein the first electrode is composed of one or more aluminum-free layers containing Ti,
wherein at least one of the two following criteria applies:
(i) the first electrode includes TiSiN; or
(ii) the first electrode includes a Ti layer having a thickness in a range of 10-80 nm and a TiN layer having a thickness in a range of 20-100 nm.

2. The semiconductor device of claim 1 , wherein the first electrode is located closer to the CMOS circuit than the second electrode.

3. The semiconductor device of claim 1 , wherein the first electrode comprises at least one of Ti or TiN.

4. The semiconductor device of claim 1 , wherein the first electrode consists essentially of a Ti/TiN stack.

5. The semiconductor device of claim 1 , wherein the first electrode has a thickness less than 150 nm inclusive.

6. The semiconductor device of claim 1 , wherein the first electrode includes the Ti layer having a thickness in a range of 50-80 nm.

7. The semiconductor device of claim 1 , wherein the first electrode includes the TiN layer having a thickness in a range of 20-100 nm.

8. The semiconductor device of claim 1 , wherein the first electrode includes the TiSiN.

9. The semiconductor device of claim 1 , wherein the second electrode includes tungsten disposed on a TiN/Ti/TiN stack.

10. The semiconductor device of claim 9 , wherein a Ti layer in the TiN/Ti/TiN stack of the second electrode has a thickness of at least 50 nm.

11. The semiconductor device of claim 9 , wherein the second electrode includes a TiN/Ti/TiN/W/Ti/TiN stack.

12. The semiconductor device of claim 1 , wherein the second electrode includes tungsten disposed on a TiSiN/Ti/TiN stack.

13. A semiconductor device comprising:
a die including a capacitive pressure sensor integrated on a CMOS circuit,
wherein the capacitive pressure sensor includes a first electrode and a second electrode separated from one another by a cavity, the second electrode including a suspended tensile membrane,
wherein the second electrode includes tungsten disposed on a TiN/Ti/TiN stack or on a TiSiN/Ti/TiN stack, and
wherein a Ti layer in the TiN/Ti/TiN stack or in the TiSiN/Ti/TiN stack of the second electrode has a thickness of at least 50 nm.

14. The semiconductor device of claim 13 , wherein the second electrode includes a TiN/Ti/TiN/W/Ti/TiN stack or a TiSiN/Ti/TiN/W/Ti/TiN stack.

15. The semiconductor device of claim 13 , wherein the second electrode is located further from the CMOS circuit than the first electrode.

16. A method comprising:
depositing and patterning layers of a first electrode on a passivation layer disposed over a CMOS circuit, wherein the layers of the first electrode are composed of one or more aluminum-free layers containing Ti;
depositing a sacrificial oxide over the first electrode;
depositing and patterning layers of a second electrode on the sacrificial oxide; and
etching part of the sacrificial oxide to form a cavity between the first and second electrodes such that the second electrode includes a suspended tensile membrane,
wherein at least one of the two following criteria applies:
(i) the first electrode includes TiSiN; or
(ii) the first electrode includes a Ti layer having a thickness in a range of 10-8 nm and a TiN layer having a thickness in a range of 20-100 nm.

17. The method of claim 16 , wherein the first electrode is a Ti/TiN stack.

18. The method of claim 16 , wherein the first electrode includes the TiSiN.

19. The method of claim 16 , wherein depositing and patterning layers of the first electrode comprises:
depositing the Ti layer for the first electrode, the Ti layer having the thickness in the range of 10-80 nm; and
subsequently depositing the TiN layer for the first electrode, the TiN layer having the thickness in the range of 20-100 nm.

20. The method of claim 16 , wherein the layers for the second electrode include tungsten disposed on a TiN/Ti/TiN stack or on a TiSiN/Ti/TiN stack.

Assignees

• Sciosense Bv

Inventors

• Besling Willem Frederik Adrianus
• Pijnenburg Remco Henricus Wilhelmus
• Vijayakumar Kailash
• Siegert Jörg
• Faes Alessandro

Classifications

• G01L9/0042 Primary

  Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms (details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively) · CPC title

• G01L9/0073 Primary

  using a semiconductive diaphragm · CPC title