Fan-out semiconductor packages

Patent metadata

Field	Value
Publication number	US-12159833-B2
Application number	US-202318151731-A
Country	US
Kind code	B2
Filing date	Jan 9, 2023
Priority date	Dec 16, 2019
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

A fan-out semiconductor package includes a frame substrate having a through hole therein, a semiconductor chip in the through hole, wherein the semiconductor chip includes a chip body, a chip pad on a surface of the chip body and a passivation layer on the chip body and on the chip pad, an encapsulation layer on side surfaces of the semiconductor chip within the through hole, and a guard ring on the passivation layer and on an edge portion of the chip body.

First claim

What is claimed is:

1. A fan-out semiconductor package comprising:
a substrate comprising a through hole therein, the through hole penetrating a top surface and a bottom surface of the substrate in a portion of the substrate;
a semiconductor chip in the through hole, wherein the semiconductor chip comprises a chip body and a chip pad on a bottom surface of the chip body;
a via penetrating a top surface and a bottom surface of the substrate in another portion of the substrate;
an encapsulation layer on side surfaces of the semiconductor chip within the through hole; and
a guard ring on the bottom surface of chip body, on an edge portion of the chip body, and in direct contact with the encapsulation layer.

2. The fan-out semiconductor package of claim 1 , wherein the guard ring comprises a continuous layer extending along a perimeter of the chip body in a plan view.

3. The fan-out semiconductor package of claim 1 , wherein the guard ring is in contact with a side surface of the encapsulation layer.

4. The fan-out semiconductor package of claim 1 , wherein a re-wiring structure that is electrically connected to the chip pad is on the bottom surface of the substrate and on a bottom surface of the semiconductor chip.

5. The fan-out semiconductor package of claim 1 , wherein—a re-wiring structure that is electrically connected to the via is on the top surface of substrate and on a top surface of the semiconductor chip.

6. The fan-out semiconductor package of claim 1 , wherein a top surface of the via is coplanar with the top surface of the substrate.

7. The fan-out semiconductor package of claim 1 , wherein a bottom surface of the via is coplanar with the bottom surface of the substrate.

8. The fan-out semiconductor package of claim 1 , wherein a bottom surface of the guard ring is coplanar with the bottom surface of the substrate.

9. The fan-out semiconductor package of claim 1 , wherein a top surface of the encapsulation layer is at a same level as a top surface of the chip body.

10. A fan-out semiconductor package comprising:
a substrate comprising a through hole therein;
a semiconductor chip in the through hole, wherein the semiconductor chip comprises a chip body, at least one chip pad on a bottom surface of the chip body;
a via penetrating a top surface and a bottom surface of the substrate;
an encapsulation layer on side surfaces of the semiconductor chip within the through hole; and
a guard ring on the bottom surface of chip body and on an edge portion of the chip body, the guard ring having a bottom surface at a level that is equal to a bottom surface of the encapsulation layer.

11. The fan-out semiconductor package of claim 10 , wherein the guard ring comprises a continuous layer extending along a perimeter of the chip body in a plan view.

12. The fan-out semiconductor package of claim 10 , wherein the guard ring is in contact with a side surface of the encapsulation layer.

13. The fan-out semiconductor package of claim 10 , wherein the bottom surface of the guard ring is coplanar with the bottom surface of the substrate.

14. The fan-out semiconductor package of claim 10 , wherein a re-wiring structure and a re-wiring pad electrically connected to the chip pad are on the bottom surface of the substrate and on a bottom surface of the semiconductor chip.

15. The fan-out semiconductor package of claim 10 , wherein a re-wiring structure that is electrically connected to the via is on the top surface of substrate and on a top surface of the semiconductor chip, and
wherein a package that is electrically connected to the via is on the re-wiring structure.

16. A fan-out semiconductor package comprising:
a substrate comprising a through hole therein, and including a top surface and a bottom surface;
a semiconductor chip in the through hole, wherein the semiconductor chip comprises a chip body, at least one chip pad on a bottom surface of the chip body, wherein the bottom surface of the chip body is at a higher level than a bottom surface of the substrate;
a via penetrating the top surface and the bottom surface of the substrate;
an encapsulation layer on side surfaces of the semiconductor chip within the through hole; and
a guard ring on the bottom surface of chip body and on an edge portion of the chip body, the guard ring having a bottom surface at a level that is equal to a bottom surface of the substrate.

17. The fan-out semiconductor package of claim 16 , wherein a top surface of the encapsulation layer is at a same level as a top surface of the chip body.

18. The fan-out semiconductor package of claim 16 , wherein the guard ring is in contact with a passivation layer.

19. The fan-out semiconductor package of claim 16 , wherein the guard ring continuously extends along a perimeter of the chip body in a plan view.

20. The fan-out semiconductor package of claim 16 , wherein the bottom surface of the via is coplanar with the bottom surface of the substrate, and wherein the top surface of the via is coplanar with the top surface of the substrate.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Joonsung
• Kim Khaile

Classifications

• H10W74/134

  the encapsulations being in grooves in the semiconductor body · CPC title

• H10W72/90

  Bond pads, in general · CPC title

• H10W70/479

  on or in insulating or insulated package substrates, interposers, or redistribution layers · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title