Independent set/reset programming scheme

Patent metadata

Field	Value
Publication number	US-9442663-B2
Application number	US-201414547473-A
Country	US
Kind code	B2
Filing date	Nov 19, 2014
Priority date	Nov 19, 2014
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

Methods for operating a non-volatile memory that includes a plurality of memory arrays in which each memory array of the plurality of memory arrays may independently perform a SET operation, a RESET operation, or a read operation are described. The ability to independently SET or RESET memory arrays allows a SET operation to be performed on a first set of memory cells within a first memory array at the same time as a RESET operation is performed on a second set of memory cells within a second memory array. In some cases, the first memory array may be associated with a first memory bay and the second memory array may be associated with a second memory bay. Each memory bay may include a memory array, read/write circuits, and control circuitry for determining memory cell groupings and programming memory cells within the memory array based on the memory cell groupings.

First claim

What is claimed is:

1. A method for operating a non-volatile storage system, comprising:
acquiring a first set of data to be programmed into a first set of memory cells within a first memory array;
acquiring a second set of data to be programmed into a second set of memory cells within a second memory array;
determining a first grouping of the first set of memory cells to be programmed from a first programming state to a second programming state;
determining a second grouping of the second set of memory cells to be programmed from the second programming state to the first programming state;
programming the first grouping of the first set of memory cells from the first programming state to the second programming state during a first programming cycle; and
programming the second grouping of the second set of memory cells from the second programming state to the first programming state during the first programming cycle.

2. The method of claim 1 , wherein:
the programming the second grouping includes programming the second grouping to the first programming state at the same time that the first grouping of the first set of memory cells is programmed to the second programming state.

3. The method of claim 1 , further comprising:
determining a plurality of groupings for the first set of memory cells associated with RESETTING the first set of memory cells over a plurality of programming cycles, the plurality of groupings includes the first grouping of the first set of memory cells.

4. The method of claim 3 , wherein:
the plurality of groupings comprises a number of groupings, the number of groupings is set based on the ceiling of a number of memory cells of the first set of memory cells to be RESET during the plurality of programming cycles divided by a maximum number of memory cells that may be simultaneously programmed during any cycle of the plurality of programming cycles.

5. The method of claim 1 , wherein:
the programming the first grouping includes configuring one or more column decoders with independent bit line to read/write circuit addressing to select the first grouping of the first set of memory cells.

6. The method of claim 1 , wherein:
the first set of data comprises a first portion of a page of data; and
the second set of data comprises a second portion of the page of data.

7. The method of claim 1 , wherein:
each memory cell of the first set of memory cells is connected to a first word line of the first memory array; and
each memory cell of the second set of memory cells is connected to a second word line of the second memory array.

8. The method of claim 1 , wherein:
the first grouping corresponds with a first set of non-contiguous bit line addresses; and
the second grouping corresponds with a second set of non-contiguous bit line addresses different from the first set of non-contiguous bit line addresses.

9. The method of claim 1 , wherein:
the programming the first grouping includes performing a RESET operation on the first memory array; and
the programming the second grouping includes performing a SET operation on the second memory array.

10. The method of claim 1 , wherein:
the first memory array comprises a non-volatile memory that is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.

11. The method of claim 1 , wherein:
the first memory array comprises a three-dimensional memory array.

12. A non-volatile storage system, comprising:
a plurality of memory arrays, the plurality of memory arrays includes a first memory array and a second memory array; and
one or more control circuits in communication with the plurality of memory arrays, the one or more control circuits configured to acquire a first set of data to be programmed into a first set of memory cells within the first memory array and configured to acquire a second set of data to be programmed into a second set of memory cells within the second memory array, the one or more control circuits configured to determine a first grouping of the first set of memory cells to be programmed from a first programming state to a second programming state and configured to determine a second grouping of the second set of memory cells to be programmed from the second programming state to the first programming state, the one or more control circuits configured to cause the first grouping of the first set of memory cells to be programmed from the first programming state to the second programming state during a first programming cycle, the one or more control circuits configured to cause the second grouping of the second set of memory cells to be programmed from the second programming state to the first programming state during the first programming cycle while the first grouping of the first set of memory cells is programmed to the second programming state.

13. The non-volatile storage system of claim 12 , wherein:
the one or more control circuits configured to determine a plurality of groupings for the first set of memory cells associated with RESETTING the first set of memory cells over a plurality of programming cycles, the plurality of groupings includes the first grouping of the first set of memory cells.

14. The non-volatile storage system of claim 13 , wherein:
the plurality of groupings comprises a number of groupings, the one or more control circuits configured to determine the number of groupings based on the ceiling of a number of memory cells of the first set of memory cells to be RESET during the plurality of programming cycles divided by a maximum number of memory cells that may be simultaneously programmed during any cycle of the plurality of programming cycles.

15. The non-volatile storage system of claim 12 , wherein:
the one or more control circuits configured to configure one or more column decoders with independent bit line to read/write circuit addressing to select the first grouping of the first set of memory cells during the first programming cycle.

16. The non-volatile storage system of claim 12 , wherein:
each memory cell of the first set of memory cells is connected to a first word line of the first memory array; and
each memory cell of the second set of memory cells is connected to a second word line of the second memory array.

17. The non-volatile storage system of claim 12 , wherein:
the first grouping corresponds with a first set of non-contiguous bit line addresses; and
the second grouping corresponds with a second set of non-contiguous bit line addresses different from the first set of non-contiguous bit line addresses.

18. The non-volatile storage system of claim 12 , wherein:
each memory cell of the first grouping is RESET during the first programming cycle; and
each memory cell of the second grouping is SET during the first programming cycle.

19. A method for operating a non-volatile storage system, comprising:
acquiring a page of data to be programmed across a plurality of memory arrays;
determining a first set of data of the page of data to be programmed into a first set of memory cells within a first memory array of the plurality of memory arrays;
determining a second set of data of the page of data to be programmed into a second set of memory cells within a second memory array of the plurality of memory arrays;
determining a first grouping of the first set of memory cells to be RESET during a first programming cycle;
determining a second grouping of the second set of memory cells to be SET during the first programmin

Assignees

• Sandisk 3D Llc
• Sandisk Technologies Llc

Inventors

• Yan Tianhong
• Liu Tz-Yi

Classifications

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title

• G06F3/0616 Primary

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title