Electronic device managing corrected error and operating method of electronic device

Patent metadata

Field	Value
Publication number	US-12158809-B2
Application number	US-202318295457-A
Country	US
Kind code	B2
Filing date	Apr 4, 2023
Priority date	Jul 4, 2022
Publication date	Dec 3, 2024
Grant date	Dec 3, 2024

Abstract

Disclosed is an electronic device including a memory module that includes at least one dynamic random access memory, and a processor configured to access the memory module, determine a corrected error count associated with an address of a corrected error in response to the corrected error being detected when data are read from the memory module, read an error log associated with the corrected error, determine a risk level of the corrected error based on the error log, and schedule a post package repair (PPR) for the address of the corrected error in response to the risk level of the corrected error being high.

First claim

What is claimed is:

1. An electronic device comprising:
a memory module including at least one dynamic random access memory; and
a processor configured to:
access the memory module,
determine a corrected error count associated with an address of a corrected error, in response to the corrected error being detected when data are read from the memory module;
read an error log associated with the corrected error;
determine a risk level of the corrected error based on the error log;
determine whether the corrected error is a temporary error based on a number of occurrences of a read error in a read retry operation;
determine the risk level of the corrected error to be low in response to determining that the corrected error is a temporary error;
determine the risk level of the corrected error to be high in response to determining that the corrected error is not a temporary error; and
schedule a post package repair (PPR) for the address of the corrected error in response to the risk level being high.

2. The electronic device of claim 1 , wherein the processor is configured to:
determine the risk level of the corrected error to be high, in response to the corrected error count associated with the address of the corrected error exceeding a threshold value.

3. The electronic device of claim 1 , wherein the processor is configured to:
request a read operation from the memory module based on the address;
request the read retry operation from the memory module in response to the read operation failing; and
detect the corrected error in response to the read retry operation succeeding.

4. The electronic device of claim 3 , wherein the processor is configured to perform the read operation by:
requesting the memory module to perform a read phase of the read operation; and
requesting the memory module to perform a retransmission phase of the read operation in response to an error occurring in the read phase.

5. The electronic device of claim 3 , wherein the processor is configured to perform the read retry operation by:
requesting the memory module to perform a first read phase to a fourth read phase until the read retry operation succeeds.

6. The electronic device of claim 5 , wherein the processor is configured to:
determine the risk level of the corrected error to be low in response to the first read phase of the read retry operation succeeding; and
determine the risk level of the corrected error to be high in response to the first read phase of the read retry operation not succeeding.

7. The electronic device of claim 3 , wherein the processor is configured to perform the read retry operation by:
requesting the memory module to perform a read phase; and
requesting the memory module to again perform the read phase N times in response to an error occurring in the read phase, N being a positive integer.

8. The electronic device of claim 5 , wherein the processor is configured to:
determine the risk level of the corrected error to be low in response to an M-th read phase of the read retry operation succeeding or a previous read phase of the M-th read phase succeeding, wherein M is a positive integer smaller than N; and
determine the risk level of the corrected error to be high in response to the M-th read phase of the read retry operation failing and the previous read phase of the M-th read phase failing.

9. The electronic device of claim 1 , wherein the processor is configured to:
collect a list of at least one address of at least one corrected error having a high risk level; and
request the PPR from the memory module based on the list of the at least one address in a next power-on sequence.

10. The electronic device of claim 1 , wherein the processor is configured to:
request the PPR from the memory module based on the address of the corrected error in response to that the risk level of the corrected error being determined to be high.

11. The electronic device of claim 10 , wherein the processor is configured to:
request, based on the address of the corrected error, the PPR from the memory module within an idle time of the memory module or before accessing the memory module.

12. The electronic device of claim 1 , wherein the processor is configured to:
determine a risk level comparison value of the corrected error in response to the risk level of the corrected error being determined to be high.

13. The electronic device of claim 12 , wherein, the processor is configured to:
request the PPR of the corrected error from the memory module in response to the risk level comparison value indicating a higher risk; and
request the PPR of the corrected error from the memory module after a next power-on in response to the risk level comparison value indicating a lower risk.

14. The electronic device of claim 12 , wherein the PPR includes a software PPR (sPPR) and a hardware PPR (hPPR), and the processor is configured to:
schedule the hardware PPR as the PPR of the corrected error in response to the risk level comparison value indicating a higher risk; and
request the software PPR as the PPR of the corrected error from the memory module in response to the risk level comparison value indicating a lower risk.

15. The electronic device of claim 14 , wherein the processor is configured to immediately request the software PPR from the memory module and requests the hardware PPR from the memory module after a next power-on.

16. An operating method of an electronic device including a processor and a memory module, the method comprising:
performing, at the processor, a read operation on the memory module;
performing, at the processor, a read retry operation on the memory module in response to an error occurring in the read operation;
determining, at the processor, a risk level of a corrected error, based on whether the corrected error occurs in any read phase of the read retry operation;
determining whether the corrected error is a temporary error based on a number of occurrences of a read error in the read retry operation;
determining the risk level of the corrected error to be low in response to determining that the corrected error is a temporary error;
determining the risk level of the corrected error to be high in response to determining that the corrected error is not a temporary error; and
scheduling, at the processor, a post package repair (PPR) of the memory module based on an address of the corrected error, in response to the risk level of the corrected error being high.

17. The method of claim 16 , wherein the scheduling of the PPR includes:
scheduling one of an immediate PPR or a delayed PPR based on a risk level comparison value of the corrected error.

18. The method of claim 16 , wherein the scheduling of the PPR includes:
scheduling one of a software PPR or a hardware PPR based on a risk level comparison value of the corrected error.

19. An electronic device comprising:
a basic input output system (BIOS) device including a nonvolatile memory storing a BIOS;
a storage device configured to store an operating system;
a chipset connected with the BIOS device and the storage device;
a memory module including at least one dynamic random access memory; and
a processor connected with the chipset and the memory module,
wherein, in a power-on, the processor is configured to:
load the BIOS from the BIOS device through the chipset; and
load the operating system from the storage device through the chipset, and

wherein, in response to a corrected error occurring when the processor acce

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Ho-Young
• Kim Sung-Joon
• Kim Ilho
• Park Kyungjin
• Yun Changho
• Jeong Jinhun
• CHOI Insu
• Han Kyung-Hee
• Kim Yukyoung
• Kim Jinwoo
• Lee Chaeeun
• Hwang Yunmi

Classifications

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F11/1438

  Restarting or rejuvenating · CPC title