Soft post package repair of memory devices

Patent metadata

Field	Value
Publication number	US-9922729-B2
Application number	US-201715703223-A
Country	US
Kind code	B2
Filing date	Sep 13, 2017
Priority date	Apr 7, 2014
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.

First claim

What is claimed is:

1. A memory device comprising:
a memory array;
a set of address terminals configured to receive address information;
a first volatile storage element configured, responsive to the memory device entering a soft post package repair mode, to store address information received at the set of address terminals as defective address data corresponding to a first address of the memory array that includes at least one defective memory cell; and
a second volatile storage element configured, responsive to the memory device exiting from the soft post package repair mode, to store address information received at the set of address terminals as access address data for the memory array.

2. The device of claim 1 , further comprising a match logic circuit configured to detect whether the access address data stored in the second volatile storage element matches the defective address data stored in the first volatile storage element.

3. The device of claim 2 , further comprising an access circuit configured to:
access a second address of the memory array that corresponds to the access address data responsive to the access address data being detected not to match the defective address data, and
access a third address of the memory array that is different than the first address responsive to the access address data being detected to match the defective address data.

4. The device of claim 3 ,
wherein the memory array comprises a plurality of data rows and at least one redundant row;
wherein the first address of the memory array designates a first data row of the plurality of data rows;
wherein the second address of the memory array designates a second data row of the plurality of data rows; and
wherein the third address of the memory array designates at least one redundant row.

5. The device of claim 3 ,
wherein the memory array comprises a plurality of data rows and a plurality of redundant rows;
wherein the first address of the memory array designates one of a first data row of the plurality of data rows and a first redundant row of the plurality of redundant rows;
wherein the second address of the memory array designates a second data row of the plurality of data rows; and
wherein the third address of the memory array designates a second redundant row of the plurality of redundant rows.

6. The device of claim 1 ,
wherein each of the defect address data and the access address data is configured to be received at the set of address terminals responsive to an activate command being asserted.

7. The device of claim 6 ,
wherein the first volatile storage element is further configured to be activated to store the defective address data responsive to the memory device entering the soft post package repair mode and to the activate command being asserted; and
wherein the second volatile storage element is further configured to be activated to store the access address data responsive to the memory device exiting from the soft post package repair mode and to the activate command being asserted.

8. A memory device comprising:
a memory array;
a non-volatile storage element configured to be programmed with first defective address data, the first defective address data designating a first address of the memory array that includes at least one defective memory cell;
a first volatile storage element configured to store, as second defective address data, address information received at the memory device during the memory device entering a soft post package repair mode, the second defective address data designating a second address of the memory array that includes at least another defective memory cell; and
a second volatile storage element configured to store, as access address data for the memory array, address information received at the memory device during the memory device exiting from the soft post package repair mode.

9. The device of claim 8 , further comprising a logic circuit configured to compare the access address data with each of the first defective address data and the second defective address data.

10. The device of claim 9 , wherein the logic circuit is further configured to provide a first match signal responsive to the access address data matching the first defective address data and configured to provide a second match signal responsive to the access address data matching the second defective address data.

11. The device of claim 9 , further comprising an access circuit configured to access a third address of the memory array designated by the access address data responsive to the access address data not matching any one of the first defective address data and the second defective address data.

12. The device of claim 9 , further comprising an access circuit configured to access a third address of the memory array that is different from each of the first and second addresses responsive to the access address data matching at least one of the first defective address data and the second defective address data.

13. A method comprising:
entering a soft post package repair mode;
receiving first address information during the soft post package repair mode;
latching the first address information in a first volatile storage element as defective address data;
exiting from the soft post package repair mode;
receiving second address information after exiting from the soft post package repair mode;
latching the second address information in a second volatile storage element as access address data; and
comparing the defective address data with the access address data to assert a match signal when the defective address data matches the access address data.

14. The method of claim 13 , further comprising:
accessing a first address of a memory array designated by the access address data when the match signal is not asserted.

15. The method of claim 13 , further comprising:
accessing a second address of a memory array that is different than the first address when the match signal is asserted.

16. The method of claim 13 ,
wherein receiving the first address information comprises receiving an activate command with the first address information; and
wherein receiving the second address information comprises receiving another activate command with the second address information.

17. The method of claim 13 , further comprising:
receiving third address information prior to entering the soft post package repair mode; and
storing the third address information into a non-volatile storage element as additional defective address data.

18. The method of claim 17 , further comprising:
comparing the additional defective address data with the access address data to assert an additional match signal when the additional defective address data matches the access address data.

19. The method of claim 18 , further comprising:
accessing an address of a memory array designated by the access address data when any one of the match signal and the additional match signal is not asserted.

20. The method of claim 18 , further comprising:
accessing an address of a memory array that is different than an address designated by each of the defective address data and the additional defective address data when at least one of the match signal and the additional match signal is asserted.

Assignees

• Micron Technology Inc

Inventors

• Wilson Alan J
• Wright Jeffrey

Classifications

• G11C11/418

  Address circuits · CPC title

• G11C17/16

  using electrically-fusible links · CPC title

• G11C11/4087

  Address decoders, e.g. bit - or word line decoders; Multiple line decoders · CPC title

• G11C29/789

  using non-volatile cells or latches · CPC title

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title