Dual inline memory provisioning and reliability, availability, and serviceability enablement based on post package repair history

Patent metadata

Field	Value
Publication number	US-10725671-B2
Application number	US-201816175555-A
Country	US
Kind code	B2
Filing date	Oct 30, 2018
Priority date	Oct 30, 2018
Publication date	Jul 28, 2020
Grant date	Jul 28, 2020

Abstract

An information handling system for DIMM provisioning and RAS enablement may include a memory subsystem that may comprise a DIMM including a set of ranks, each rank of the set of ranks may include a set of DRAMs, each DRAM of the set of DRAMs including a set of rows, and a non-volatile memory associated with the DIMM. The DIMM may include a post package repair (PPR) history including a set of PPR history entries. Each PPR history entry of the set of PPR history entries may include a failed row count for each rank of a corresponding DRAM of the DIMM. The information handling system may also include a BIOS that may determine whether health of the DIMM is unhealthy that may be based on the PPR history. When the health of the DIMM may be unhealthy, the BIOS may also perform a PPR corrective action procedure.

First claim

What is claimed is:

1. An information handling system, comprising:
a memory subsystem including:
a dual in-line memory module (DIMM) comprising:
a set of ranks, each rank of the set of ranks including a set of dynamic random-access memories (DRAMs), each DRAM of the set of DRAMs including a set of rows; and

a non-volatile memory associated with the DIMM comprising:
a post package repair (PPR) history including a set of PPR history entries, each PPR history entry of the set of PPR history entries comprising:
a failed row count for each rank of the set of rows of a corresponding DRAM of the DIMM; and

a basic input/output system (BIOS) configured to:
determine whether health of the DIMM is unhealthy based on the failed row count for each rank of the corresponding DRAM of each PPR history entry of the PPR history; and
when the health of the DIMM is unhealthy, perform a PPR corrective action procedure.

2. The information handling system of claim 1 , wherein, to perform the PPR corrective action procedure, the BIOS is further configured to:
when a first failed row count of a first rank of a first DRAM of the set of DRAMs is greater than zero, a second failed row count of the first rank of a second DRAM of the set of DRAMs is greater than zero, and a sum of the first failed row count and the second failed row count exceeds a PPR-repaired threshold:
map-out a failing row of the set of rows of the first rank of the first DRAM using a spare row of the first DRAM; and
map-out a failing row of the set of rows of the first rank of the second DRAM using a spare row of the second DRAM.

3. The information handling system of claim 1 , wherein, to perform the PPR corrective action procedure, the BIOS is further configured to:
when a first failed row count of a first rank of a first DRAM of the set of DRAMs is greater than one and a second failed row count of a second rank of the first DRAM is greater than one:
map-out a failing row of the set of rows of the first rank of the first DRAM using device tagging.

4. The information handling system of claim 1 , wherein, to perform the PPR corrective action procedure, the BIOS is further configured to:
when a first failed row count of a first rank of a first DRAM of the set of DRAMs is greater than zero and a second failed row count of a second rank of a second DRAM of the set of DRAMs is greater than zero:
decrease an operating speed of the DIMM.

5. The information handling system of claim 1 , wherein, to perform the PPR corrective action procedure, the BIOS is further configured to:
set a failure period threshold based on the PPR history, and wherein
when a first failure event occurs in a first row of a first rank of the set of rows of a first corresponding DRAM and the first failure event occurs within the failure period threshold of an occurrence of a previous failure event in a second row of the first rank of the set of rows of the first corresponding DRAM, ignore the first failure event.

6. The information handling system of claim 1 , wherein, when a first failure event occurs in a first row of a first rank of the set of rows of a first corresponding DRAM, increment the failed row count for the first rank of the set of rows of the first corresponding DRAM.

7. The information handling system of claim 1 , wherein the memory subsystem further comprising a serial presence detect (SPD) module including the non-volatile memory.

8. The information handling system of claim 1 , wherein each PPR history entry of the PPR history further comprises a failed DRAM identification of the corresponding DRAM, and wherein each PPR history entry of the set of PPR history entries has at least one failed row count for each rank of the corresponding DRAM greater than zero.

9. The information handling system of claim 1 , wherein, to perform the PPR corrective action procedure, the BIOS is further configured to store an address of a failing row of the set of rows of the rank of the corresponding DRAM.

10. The information handling system of claim 1 , wherein the BIOS is further configured to: determine a runtime behavior of the DIMM, wherein the runtime behavior of the DIMM includes at least one of an operating time of the DIMM, a number of failures, and a rate of degradation; and
perform the PPR corrective action procedure based at least on the runtime behavior of the DIMM.

11. The information handling system of claim 1 , wherein, to perform the PPR corrective action procedure, the BIOS is further configured to send a DIMM corrective action message to a user of the information handling system, wherein the DIMM corrective action message based on the PPR history of the DIMM and indicates that the DIMM should be replaced.

12. A method, comprising:
determining, by a basic input/output system (BIOS) of the information handling system, whether health of a dual in-line memory module (DIMM) of a memory subsystem of an information handling system is unhealthy based on a post package repair (PPR) history, wherein
the DIMM comprising a set of ranks, each rank of the set of ranks including a set of dynamic random-access memories (DRAMs), each dynamic random-access memory (DRAM) of the set of DRAMs including a set of rows, and wherein
the PPR history stored at a non-volatile memory of the memory subsystem associated with the DIMM and including a set of PPR history entries, each PPR history entry of the set of PPR history entries comprising a failed row count for each rank of the set of rows of a corresponding DRAM of the DIMM; and

when the health of the DIMM is unhealthy, performing, by the BIOS, a PPR correction action procedure.

13. The method of claim 12 , wherein the performing the corrective action procedure comprises:
when a first failed row count of a first rank of a first DRAM of the set of DRAMs is greater than zero, a second failed row count of the first rank of a second DRAM of the set of DRAMs is greater than zero, and a sum of the first failed row count and the second failed row count exceeds a PPR-repaired threshold:
mapping-out a failing row of the set of rows of the first rank of the first DRAM using a spare row of the first DRAM; and
mapping-out a failing row of the set of rows of the first rank of the second DRAM using a spare row of the second DRAM.

14. The method of claim 13 , wherein the performing the corrective action procedure further comprises:
when a first failed row count of a first rank of a first DRAM of the set of DRAMs is greater than one and a second failed row count of a second rank of the first DRAM is greater than one:
mapping-out a failing row of the set of rows of the first rank of the first DRAM using device tagging.

15. The method of claim 13 , wherein the performing the corrective action procedure further comprises:
when a first failed row count of a first rank of a first DRAM of the set of DRAMs is greater than zero and a second failed row count of a second rank of a second DRAM of the set of DRAMs is greater than zero:
decreasing an operating speed of the DIMM.

16. The method of claim 13 , wherein the performing the corrective action procedure further comprises:
setting a failure period threshold based on the PPR history; and
when a first failure event occurs in a first row of a first rank of the set of rows of a first corresponding DRAM and the first failure event occurs within the failure period threshold of an occurrence of a previous failure event in a second row of the first rank of the set of rows of the first corresponding DRAM, ignoring the first failure event.

17. The method of

Assignees

• Dell Products Lp

Inventors

• Shah Amit Sumanlal
• Mukherjee Ananya
• Farley Mark Lawrence
• Sankaranarayanan Vadhiraj

Classifications

• G06F11/1417

  Boot up procedures · CPC title

• G06F11/076 Primary

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G06F11/0793

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title