Thin film transistor array substrate and organic light-emitting diode display

Patent metadata

Field	Value
Publication number	US-12150345-B2
Application number	US-202218057139-A
Country	US
Kind code	B2
Filing date	Nov 18, 2022
Priority date	Sep 19, 2012
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

A thin film transistor (TFT) array substrate includes: a substrate; a first insulation layer on the substrate; a capacitor including a lower electrode on the first insulation layer, and an upper electrode arranged to overlap with the whole lower electrode and having an opening, and the upper electrode is insulated from the lower electrode by a second insulation layer; an inter-layer insulation film covering the capacitor; a node contact hole in the inter-layer insulation film and the second insulation layer, and within the opening; and a connection node on the inter-layer insulation film and electrically coupling the lower electrode and at least one TFT to each other through the node contact hole.

First claim

What is claimed is:

1. A display device comprising:
a substrate;
a first scan line disposed on the substrate, the first scan line extending in a first direction;
a data line crossing the first scan line, the data line extending in a second direction;
a driving voltage line crossing the first scan line;
an organic light emitting diode (OLED) including a first electrode, an organic light-emitting layer and a second electrode; and
a pixel circuit coupled to the organic light emitting diode, wherein the pixel circuit comprises:
a first thin film transistor including a first channel region, a third electrode coupled to the first channel region, a fourth electrode coupled to the first channel region, and a first gate electrode overlapping the first channel region in a plan view, wherein the first thin film transistor is coupled to the organic light emitting diode;
a second thin film transistor including a second channel region, a fifth electrode coupled to the second channel region, a sixth electrode coupled to the second channel region, and a second gate electrode overlapping the second channel region in the plan view, wherein the second gate electrode is coupled to the first scan line; and
a storage capacitor including the first gate electrode and a first metal pattern overlapping the first gate electrode in the plan view, the first metal pattern being coupled to the driving voltage line,
wherein all of the first channel region, the first gate electrode, and the first metal pattern are overlapped with each other in the plan view, the first metal pattern and the data line are overlapped with each other in the plan view, the first metal pattern and the driving voltage line are overlapped with each other in the plan view, and
wherein an entire area of a first portion in which the first metal pattern and the data line are overlapped with each other is smaller than an entire area of a second portion in which the first metal pattern and the driving voltage line are overlapped with each other.

2. The display device of claim 1 , wherein the first metal pattern comprises an opening.

3. The display device of claim 2 , wherein the pixel circuit further comprises a first connection member, the first connection member couples the first gate electrode and the fifth electrode, and an end portion of the first connection member is disposed within the opening.

4. The display device of claim 3 , wherein the first connection member and the first metal pattern are overlapped with each other in the plan view.

5. The display device of claim 4 , wherein the first connection member and the first electrode are overlapped with each other in the plan view, and the connection member disposed between the first metal pattern and the first electrode in a cross-sectional view.

6. The display device of claim 4 , wherein the first connection member is disposed on a same layer as the data line or the driving voltage line.

7. The display device of claim 3 , wherein the display device further comprises a node contact hole within the opening, and wherein at least a portion of the first connection member is coupled to the first gate electrode through the node contact hole, and the node contact hole is defined by at least one insulating layer between the first gate electrode and the first connection member.

8. The display device of claim 7 , wherein a size of the opening is greater than a size of the node contact hole in the plan view.

9. The display device of claim 3 , wherein the first connection member crosses the first scan line.

10. The display device of claim 3 , wherein a longest length of the first portion in the second direction is smaller than a longest length of the second portion in the second direction.

11. The display device of claim 10 , wherein a greatest width of the first portion in the first direction is smaller than a greatest width of the second portion in the first direction.

12. The display device of claim 3 , wherein an entire area of a third portion in which the first gate electrode and the driving voltage line are overlapped with each other in the plan view is smaller than the entire area of the second portion.

13. The display device of claim 12 , a greatest width of the first portion in the first direction is smaller than a greatest width of the second portion in the first direction.

14. The display device of claim 3 , wherein the display device further comprises a first contact hole, the first metal pattern and the driving voltage line are coupled to each other through the first contact hole and the first contact hole is defined by at least one insulating layer between the first metal pattern and the driving voltage line.

15. The display device of claim 14 , wherein the first contact hole is overlapped with the first gate electrode.

16. The display device of claim 15 , wherein the first contact hole is overlapped with the first channel region.

17. The display device of claim 3 , wherein the pixel circuit has a portion in which all of the first channel region, the first gate electrode, the first metal pattern and the driving voltage line are overlapped with each other.

18. The display device of claim 3 , wherein the fourth electrode and the sixth electrode are integral in a body and wherein the fourth electrode is extended from the first channel region, and the sixth electrode is extended from the second channel region.

19. The display device of claim 3 , wherein the display device further comprises a second scan line and an initialization voltage line, the second scan line and the initialization voltage line cross the data line.

20. The display device of claim 19 , wherein the pixel circuit further comprises a third thin film transistor including a third channel region, a seventh electrode coupled to the third channel region, an eighth electrode coupled to the third channel region, and the third gate electrode overlapping the third channel region in the plan view, wherein the third gate electrode is coupled to the second scan line, wherein the eighth electrode coupled to the initialization voltage line, and the seventh electrode and the fifth electrode are integral in a body.

21. The display device of claim 20 , wherein the eighth electrode coupled to the initialization voltage line via a second connection member.

22. The display device of claim 20 , wherein the pixel circuit further comprises a fourth thin film transistor including a fourth channel region, a ninth electrode coupled to the fourth channel region, a tenth electrode coupled to the fourth channel region, and a fourth gate electrode overlapping the fourth channel region in the plan view, wherein the fourth gate electrode is coupled to the first scan line, the ninth electrode is coupled to the data line, and the tenth electrode is electrode is coupled to the third electrode of the first thin film transistor.

23. The display device of claim 19 , wherein the pixel circuit further comprises a third thin film transistor including a third channel region, a seventh electrode coupled to the third channel region, an eighth electrode coupled to the third channel region, and a third gate electrode overlapping the third channel region in the plan view, wherein the third gate electrode is coupled to the second scan line, and the seventh electrode and the first gate electrode are coupled to each other via the first connection member.

24. The display device of claim 23 , wherein the eighth electrode is coupl

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Won-Se
• Kwak Won-Kyu
• Kim Se-Ho

Classifications

• H10K59/10

  OLED displays · CPC title

• H10K59/1216 Primary

  the pixel elements being capacitors · CPC title

• H10D86/481 Primary

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D1/68

  Capacitors having no potential barriers · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title