Organic light emitting diode display

Patent metadata

Field	Value
Publication number	US-9570534-B2
Application number	US-201514946231-A
Country	US
Kind code	B2
Filing date	Nov 19, 2015
Priority date	Jun 30, 2010
Publication date	Feb 14, 2017
Grant date	Feb 14, 2017

Abstract

An organic light emitting diode display includes: a substrate including a first and a second gate electrode formed over a first and a second region, respectively, a first and a second gate insulator formed on the first and the second gate electrode, respectively, a first and a second semiconductor layer formed on the first and the second gate insulator, respectively, the first semiconductor layer including a first channel region, the second semiconductor layer including a second channel region, an interlayer insulator formed over the substrate and over at least part of the first and second semiconductor layers, a first and a second etching stop layer formed over the first and second channel regions, respectively, and surrounded by the interlayer insulator, and a first and a second source electrode and a first and a second drain electrode contacting the first and the second semiconductor layer, respectively, through the interlayer insulator.

First claim

What is claimed is:

1. An organic light emitting diode display, comprising:
a substrate including a first region, a second region and a third region, wherein the third region includes a lower capacitor electrode, a dielectric layer, and a first upper capacitor electrode;
a first gate electrode formed over the first region;
a second gate electrode formed over the second region;
a first gate insulator formed on the first gate electrode;
a second gate insulator formed on the second gate electrode;
a first semiconductor layer formed on the first gate insulator, the first semiconductor layer comprising a first channel region;
a second semiconductor layer formed on the second gate insulator, the second semiconductor layer comprising a second channel region;
an interlayer insulator formed over the substrate and over at least part of the first and second semiconductor layers;
a first etching stop layer formed over the first channel region and surrounded by the interlayer insulator;
a second etching stop layer formed over the second channel region and surrounded by the interlayer insulator;
a first source electrode and a first drain electrode contacting the first semiconductor layer through the interlayer insulator;
a second source electrode and a second drain electrode contacting the second semiconductor layer through the interlayer insulator;
a passivation layer formed over at least part of the first source electrode, the first drain electrode, the second source electrode and the second drain electrode; and
a gate line formed over the passivation layer and electrically connected with the first gate electrode through the passivation layer and further through the first gate insulator,
wherein the first upper capacitor electrode is coplanar with the first semiconductor layer.

2. The organic light emitting diode display of claim 1 , further comprising:
a first connection wire formed on the passivation layer and electrically connected with the second gate electrode through the passivation layer and further through the second gate insulator.

3. The organic light emitting diode display of claim 2 , wherein:
the first connection wire is electrically connected with the first drain electrode.

4. The organic light emitting diode display of claim 3 , further comprising:
pixel electrode material layer patterns formed on the gate line, the first connection wire, and a second connection wire, respectively.

5. The organic light emitting diode display of claim 1 , further comprising:
a second connection wire formed on the passivation layer and electrically connected with the second drain electrode through the passivation layer.

6. The organic light emitting diode display of claim 5 , further comprising:
a pixel electrode formed on the passivation layer and electrically connected with the second connection wire.

7. The organic light emitting diode display of claim 1 , wherein:
each of the first and second gate electrodes comprises a doped or undoped amorphous silicon layer or a doped or undoped polysilicon layer.

8. The organic light emitting diode display of claim 1 , wherein:
the lower capacitor electrode is electrically connected with the second gate electrode.

9. The organic light emitting diode display of claim 1 , wherein:
the lower capacitor electrode comprises a doped or undoped amorphous silicon layer or a doped or undoped polysilicon layer.

10. The organic light emitting diode display of claim 1 , further comprising:
a second upper capacitor electrode formed on the interlayer insulator and electrically connected with the first upper capacitor electrode.

11. The organic light emitting diode display of claim 10 , wherein:
the second upper capacitor electrode comprises a lamination structure of a silicon layer pattern injected with high-concentration impurities and a metallic layer pattern.

Assignees

• Samsung Display Co Ltd

Inventors

• Cho Kyu-Sik
• Lee Won-Kyu
• Yang Tae-Hoon
• Choo Byoung-Kwon
• Moon Sang-Ho
• Choi Bo-Kyung
• Park Yong-Hwan
• Choi Joon-Hoo
• Shin Min-Chul
• Lee Yun-Gyu

Classifications

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/1315

  comprising structures specially adapted for lowering the resistance · CPC title

• H10D30/6739

  Conductor-insulator-semiconductor electrodes · CPC title

• H10D86/451 Primary

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title