Method to integrate DC and RF phase change switches into high-speed SiGe BiCMOS

Patent metadata

Field	Value
Publication number	US-12150316-B2
Application number	US-202217981744-A
Country	US
Kind code	B2
Filing date	Nov 7, 2022
Priority date	Aug 19, 2019
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

A method of integrating a phase change switch (PCS) into a Bipolar (Bi)/Complementary Metal Oxide Semiconductor (CMOS) (BiCMOS) process, comprises providing a base structure including BiCMOS circuitry on a semiconductor substrate, and forming on the base structure a dielectric contact window layer having metal through-plugs that contact the BiCMOS circuitry. The method includes constructing the PCS on the contact window layer. The PCS includes: a phase change region, between ohmic contacts on the phase change region, to operate as a switch controlled by heat. The method further includes forming, on the contact window layer and the PCS, a stack of alternating patterned metal layers and dielectric layers that interconnect the patterned metal layers, such that the stack connects a first of the ohmic contacts to the BiCMOS circuitry and provides connections to a second of the ohmic contacts and to the resistive heater.

First claim

What is claimed is:

1. A method of integrating a phase change switch (PCS) into a Bipolar (Bi)/Complementary Metal Oxide Semiconductor (CMOS) (BiCMOS) process, comprising:
providing a base structure including BiCMOS circuitry on a semiconductor substrate;
providing a dielectric layer only over a PCS region of the semiconductor substrate that is adjacent to the BiCMOS circuitry;
forming on the base structure a contact window layer that is a dielectric and having metal through-plugs that contact the BiCMOS circuitry;
constructing the PCS on the contact window layer over the PCS region of the semiconductor substrate, the PCS including: a phase change region, connected between ohmic contacts that are spaced-apart and formed on the phase change region, configured to operate as an in-line switch connected between the ohmic contacts and that is controlled by heat applied to the phase change region; and a resistive heater to generate the heat responsive to a control signal applied to the resistive heater; and
forming, on the contact window layer and the PCS, a stack of alternating patterned metal layers and dielectric layers having metal through-plugs to interconnect the patterned metal layers, such that the stack connects a first of the ohmic contacts to the BiCMOS circuitry and provides respective connections to a second of the ohmic contacts and to the resistive heater.

2. The method of claim 1 , wherein constructing the PCS includes:
forming in the contact window layer, over the PCS region, a metal through-plug configured to serve as the resistive heater.

3. The method of claim 2 , wherein constructing the PCS further includes:
forming a dielectric barrier layer on the metal through-plug configured to serve as the resistive heater;
forming the phase change region on the dielectric barrier layer; and
forming the ohmic contacts on correspondingly spaced-apart ends of the phase change region.

4. The method of claim 2 , further comprising:
forming an insulating layer between the PCS region of the semiconductor substrate and the metal through-plug configured to serve as the resistive heater.

5. The method of claim 4 , wherein constructing the PCS further includes:
forming a passivation layer on the phase change region between the ohmic contacts.

6. The method of claim 1 , wherein constructing the PCS further includes forming ohmic contacts on the resistive heater to receive the control signal, wherein forming the stack includes forming the stack to provide respective ones of the respective connections to the ohmic contacts formed on the resistive heater.

7. The method of claim 1 , wherein the BiCMOS circuitry includes a heterojunction bipolar transistor (HBT) including a power terminal, a base, an emitter, and a collector, and forming the stack includes forming the stack such that the stack connects the first of the ohmic contacts to the power terminal, the base, the emitter, or the collector of the HBT.

8. The method of claim 1 , wherein the contact window layer comprises Tetraethyl Orthosilicate (TEOS).

9. The method of claim 1 , wherein the phase change region comprises a layer of Germanium Telluride (GeTe).

10. The method of claim 1 , wherein forming the contact window layer on the base structure and forming the PCS on the contact window layer forms a structure having no patterned metal layers and no dielectric layers with embedded metal through-plugs therein between the PCS and the BiCMOS circuitry, except for the contact window laver.

11. A method of integrating a phase change switch (PCS) into a Bipolar (Bi)/Complementary Metal Oxide Semiconductor (CMOS) (BiCMOS) process, comprising:
providing a base structure including BiCMOS circuitry on a semiconductor substrate;
providing a dielectric layer only over a PCS region of the semiconductor substrate that is adjacent to the BiCMOS circuitry;
forming on the base structure a contact window layer that is a dielectric and having metal through-plugs that contact the BiCMOS circuitry;
constructing the PCS on the contact window layer over the PCS region of the semiconductor substrate that is adjacent to the BiCMOS circuitry, wherein constructing includes:
forming a metal through-plug in the contact window layer over the PCS region;
forming a phase change region over the metal through-plug;
forming ohmic contacts that are spaced-apart on the phase change region, wherein the phase change region is configured to operate as an in-line switch connected between the ohmic contacts and that is controlled by heat applied to the phase change region, and wherein the metal through-plug is configured to generate the heat responsive to a control signal applied to the metal through-plug; and

forming, on the contact window layer and the PCS, a stack of alternating patterned metal layers and dielectric layers having metal through-plugs to interconnect the patterned metal layers, such that the stack connects a first of the ohmic contacts to the BiCMOS circuitry and provides respective connections to a second of the ohmic contacts and to the metal through-plug.

Assignees

• Northrop Grumman Systems Corp

Inventors

• Shea Patrick B
• Young Robert M
• Chung Keith H
• Ezis Andris
• Wathuthanthri Ishan

Classifications

• H10D84/401

  Combinations of FETs or IGBTs with BJTs · CPC title

• H10D84/0109

  the at least one component covered by H10D12/00 or H10D30/00 being a MOS device · CPC title

• H10D84/038 Primary

  using silicon technology, e.g. SiGe · CPC title

• H10B63/00 Primary

  Resistance change memory devices, e.g. resistive RAM [ReRAM] devices · CPC title

• H10B63/10

  Phase change RAM [PCRAM, PRAM] devices · CPC title