Multiplexer with highly linear analog switch

Patent metadata

Field	Value
Publication number	US-12149241-B2
Application number	US-202318334989-A
Country	US
Kind code	B2
Filing date	Jun 14, 2023
Priority date	Dec 2, 2020
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

First claim

The invention claimed is:

1. A multiplexer, comprising:
an output terminal;
a plurality of input terminals; and
a plurality of switch circuits each coupled between the output terminal and a respective input terminal, each switch circuit including:
a main transistor coupled between the respective input terminal and the output terminal;
a first boot strap circuit including a first bootstrap capacitor and configured to selectively couple and decouple the first bootstrap capacitor between a gate terminal and a source terminal of the main transistor; and
a second boot strap circuit including a second bootstrap capacitor and configured to selectively couple and decouple the second bootstrap capacitor between a gate terminal and a source terminal of the main transistor.

2. The multiplexer of claim 1 , wherein, for each switch circuit, the first boot strap circuit is configured to:
couple the first bootstrap capacitor between the gate terminal and the source terminal of the main transistor during a first phase and to decouple the first bootstrap capacitor from between the source terminal and the gate terminal of the main transistor during a second phase; and
couple the second bootstrap capacitor between the gate terminal and the source terminal of the main transistor during the second phase and to decouple the second bootstrap capacitor from between the source terminal and the gate terminal of the main transistor during the first phase.

3. The multiplexer of claim 2 , wherein for each switch circuit, the first boot strap circuit receives a first phase signal and the second boot strap circuit receives a second phase signal.

4. The multiplexer of claim 3 , wherein the first phase signal and the second phase signals are square waves 180 degrees out of phase with each other.

5. The multiplexer of claim 2 , wherein during the first phase the second bootstrap capacitor charges to a supply voltage value, wherein during the second phase the first bootstrap capacitor charges to the supply voltage value.

6. The multiplexer of claim 5 , wherein the first bootstrap circuit includes a plurality of first switches configured to selectively couple and decouple the first bootstrap capacitor between the gate and source terminals of the transistor during the first and second phases.

7. The multiplexer of claim 6 , wherein the second bootstrap circuit includes a plurality of second switches configured to selectively couple and decouple the second bootstrap capacitor between the gate and source terminals of the main transistor during the first and second phases.

8. The multiplexer of claim 7 , wherein the first and second phases alternate in accordance with a clock signal.

9. The multiplexer of claim 6 , wherein the first and second bootstrap circuits collectively maintain a gate to source voltage of the transistor at a constant value during the first and second phases.

10. The multiplexer of claim 9 , wherein the constant value is the supply voltage value.

11. A method, comprising:
selecting a switch circuit from a plurality of switch circuits of a multiplexer including a plurality of input terminals and an output terminal, each switch circuit coupled between a respective input terminal and the output terminal, each switch circuit including, a main transistor coupled between the input terminal and the output terminal of the multiplexer, a first bootstrap circuit, and a second bootstrap circuit;
passing a signal from the input terminal coupled to the selected switch circuit through the main transistor of the selected switch circuit to the output terminal of the multiplexer;
coupling the first bootstrap circuit of the selected switch circuit between a gate terminal and a source terminal of the main transistor of the selected switch circuit during a first phase; and
coupling the second bootstrap circuit between the gate terminal and the source terminal of the main transistor of the selected switch circuit during a second phase alternating with the first phase.

12. The method of claim 11 , further comprising:
decoupling the first bootstrap capacitor from the gate and source terminals of the selected switch circuit during the second phase; and
decoupling the second bootstrap capacitor from the gate and source terminals of the selected switch circuit during the first phase.

13. The method of claim 12 , further comprising:
charging the first capacitor of the selected switch circuit to a supply voltage value during the second phase; and
charging the second capacitor of the selected switch circuit to the supply voltage value during the first phase.

14. The method of claim 13 , further comprising maintaining a gate to source voltage of the main transistor of the selected switch circuit at the supply voltage value during the first and second phases.

15. The method of claim 14 , further comprising alternating between the first and second phases based on a clock signal.

16. The method of claim 15 , wherein coupling and decoupling the first bootstrap capacitor of the selected switch circuit includes controlling a plurality of first switches of the selected switch circuit based on the clock signal.

17. The method of claim 16 , wherein coupling and decoupling the second bootstrap capacitor of the selected switch circuit includes controlling a plurality of second switches of the selected switch circuit based on the clock signal.

18. An integrated circuit, comprising:
a multiplexer, including:
a plurality of inputs;
an output;
a plurality of switch circuits coupled between an output terminal and a respective input terminal, each switch circuit including:
a main transistor having a source terminal coupled to the input, a drain terminal coupled to the output, and a gate terminal;
a first bootstrap circuit having a first capacitor configured to be selectively coupled to and decoupled from the input; and

a second bootstrap circuit having a second capacitor configured to be selectively coupled to and decoupled from the input.

19. The integrated circuit of claim 18 , further comprising an analog-to-digital converter configured to receive a signal from the output and to convert the signal to a digital signal.

20. The integrated circuit of claim 18 , wherein the first boot strap circuit receives a first clock signal, a second clock signal, and a first phase signal 180 degrees out of phase with the first clock signal, wherein the second boot strap circuit receives the first clock signal, the second clock signal, and a second phase signal 180 degrees out of phase with the second clock signal.

Assignees

• St Microelectronics Int Nv

Inventors

• Garg Vaibhav
• Jain Abhishek
• Kumar Anand

Classifications

• H03K19/01735

  by bootstrapping, i.e. by positive feed-back · CPC title

• H03K17/693 Primary

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

• H03K17/6874

  in a symmetrical configuration · CPC title

• H03K2217/0054

  Gating switches, e.g. pass gates · CPC title

• H03K17/6872 Primary

  using complementary field-effect transistors · CPC title