Analog multiplexer

Patent metadata

Field	Value
Publication number	US-10200041-B2
Application number	US-201615340423-A
Country	US
Kind code	B2
Filing date	Nov 1, 2016
Priority date	Nov 1, 2016
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

An analog multiplexer may be used for sampling an input voltage that is capable of having a higher voltage level than an upper supply voltage. The analog multiplexer includes a plurality of input switch circuits and a shorting switch circuit. The plurality of input switch circuits include n-type or p-type laterally diffused field effect transistors (NLDFETs or PLDFETs). At least one of the input switch circuits includes a level shifting switch circuit that is able to sample an input voltage that is greater than the upper supply voltage for the multiplexer. A shorting switch circuit, at an output of the multiplexer, includes a capacitively coupled gate drive circuit and is configured to short a first differential output to a second differential output after the input voltage is sampled.

First claim

What is claimed is:

1. An analog multiplexer for sampling an input voltage capable of having a higher voltage level than an upper supply voltage of the multiplexer, the multiplexer comprising:
a plurality of input switch circuits, each input switch circuit coupled between a respective input and one of a first or a second differential output, at least one of the plurality of input switch circuits comprising a level shifting switch circuit configured to sample the input voltage capable of having the higher voltage level than the upper supply voltage; and
a shorting switch circuit coupled between the first and second differential outputs; the shorting switch circuit comprising a capacitively coupled gate drive circuit and configured to short the first differential output to the second differential output after the input voltage is sampled.

2. The analog multiplexer of claim 1 , wherein the level shifting switch circuit comprises:
a laterally diffused field effect transistor (LDFET) coupled between the respective switch input and the first differential output; and
a gate driver circuit coupled to a gate of the LDFET and configured to generate a gate control signal; the gate driver circuit comprising a plurality of level shifter circuits coupled together in a cascade configuration and coupled to the upper supply voltage and the respective switch input.

3. The analog multiplexer of claim 2 , wherein one or more of the plurality of input switch circuits comprises:
a first LDFET and a second LDFET, the first LDFET having a source node coupled to a source node of the second LDFET, the first LDFET and the second LDFET each having a gate coupled to another gate driver circuit.

4. The analog multiplexer of claim 1 , wherein one or more of the plurality of input switch circuits comprises:
a first LDFET and a second LDFET, the first LDFET having a source node coupled to a source node of the second LDFET, the first LDFET and the second LDFET each having a gate coupled to a gate driver circuit.

5. The analog multiplexer of claim 4 , wherein the one or more of the plurality of input switch circuits further comprises a refresh current source coupled to the source nodes of the first and second LDFETs and configured to generate a current pulse into the source nodes during a voltage sampling operation.

6. The analog multiplexer of claim 1 , wherein the shorting switch circuit comprises:
a first LDFET and a second LDFET, the first LDFET having a source node coupled to a source node of the second LDFET; and
the capacitively coupled gate driver circuit coupled to gates of each of the first and second LDFETs.

7. The analog multiplexer of claim 1 , further comprising an analog-to-digital converter sampling circuit coupled to the first and second differential outputs.

8. The analog multiplexer of claim 1 , in combination with a plurality of batteries coupled together in a series configuration wherein the level shifting switch circuit is coupled to an end battery in the series connected batteries and each remaining input switch circuit s coupled to a respective node either between a pair of adjacent batteries or at a last battery of the plurality of batteries.

9. The analog multiplexer of claim 1 , wherein the shorting switch circuit for shorting the first differential output to the second differential output comprises:
a plurality of laterally diffused field effect transistors (LDFETs), a first LDFET of the plurality of LDFETs having a drain coupled to a first voltage node and a source coupled to a source of a second LDFET of the plurality of LDFETs, a drain of the second LDFET coupled to a second voltage node; and
a gate driver circuit coupled to gates of the first and second LDFETs, the gate driver circuit comprising:
a voltage selector circuit having inputs coupled to the first and second voltage nodes;
a voltage drop element coupled between an output of the voltage selector circuit and a gate output;
a control signal capacitively coupled to the gate output; and
a current source coupled between the gate output and a supply node.

10. The analog multiplexer of claim 9 , wherein the voltage drop element comprises a diode having an anode coupled to the output of the voltage selector circuit and a cathode coupled to the gate output.

11. The analog multiplexer of claim 9 , wherein the voltage selector circuit is configured to output the lowest of a first voltage on the first voltage node or a second voltage on the second voltage node.

12. The analog multiplexer of claim 1 , wherein the level-shifting switch circuit comprises:
a current level shifting circuit coupled to an input voltage node and the upper supply voltage, the circuit further comprising a set input, a reset input, an elevated ground, and a gate output;
a transistor having a source coupled to the input voltage node, a drain coupled to an output voltage node, and a gate coupled to the gate output;
a voltage drop element coupled between the upper supply voltage and the elevated ground of the current level shifting circuit;
a first current source coupled between the elevated ground and a lower supply voltage;
a first switch coupled between the set input and a second current source; and
a second switch coupled between the reset input and the second current source, wherein the second current source is further coupled to the lower supply voltage.

13. The analog multiplexer of claim 12 , wherein the transistor is a laterally diffused field effect transistor (LDFET).

14. The analog multiplexer of claim 12 , wherein the voltage drop element comprises a plurality of diodes coupled in series configuration wherein an anode of first diode is coupled to the upper supply voltage and a cathode of a second diode is coupled to the elevated ground.

15. The analog multiplexer of claim 12 , wherein the current level shifting circuit is configured to generate a gate voltage that turns on the transistor in response to a current on the reset input.

16. The analog multiplexer of claim 12 , wherein the current level shifting circuit is configured to generate a gate voltage that turns off the transistor in response to a current on the set input.

17. A method for sampling an input voltage capable of having a higher voltage level than an upper supply voltage, the method comprising:
activating a level shifting switch circuit between a first input voltage node and a first differential output terminal wherein the first input voltage node comprises the input voltage having a higher voltage level than the upper supply voltage;
activating an input switch circuit between a second input voltage node and a second differential output terminal; and
shorting the first differential output terminal to the second differential output terminal after sampling of the input voltage.

18. The method of claim 17 , further comprising:
sequentially activating different pairs of input switch circuits of a plurality of input switch circuits such that a voltage on the first differential output terminal is higher than a voltage on the second differential output terminal at a first time and the voltage on the second differential output terminal is higher than the voltage on the first differential output terminal at a second time responsive to activation of different combinations of pairs of input switch circuits.

19. The method of claim 18 , further comprising converting a differential voltage at the first and second differential output terminals to a digital representation.

20. An analog multiplexer for sampling

Assignees

• Gorbold Jeremy R
• Birk Christian Steffen
• Puchalt Gerard Mora
• Price Colin Charles
• Coln Michael C W
• Kumbaranthodiyil Mahesh Madhavan
• Analog Devices Global

Inventors

• Gorbold Jeremy R
• Birk Christian Steffen
• Puchalt Gerard Mora
• Price Colin Charles
• Coln Michael C W
• Kumbaranthodiyil Mahesh Madhavan

Classifications

• H03K17/693 Primary

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

• H03K19/018507 Primary

  Interface arrangements · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03K2217/0054

  Gating switches, e.g. pass gates · CPC title

• H03K17/063

  in field-effect transistor switches · CPC title