Bootstrapped sampling switch circuits and systems

Patent metadata

Field	Value
Publication number	US-9287862-B2
Application number	US-201414533787-A
Country	US
Kind code	B2
Filing date	Nov 5, 2014
Priority date	Dec 26, 2013
Publication date	Mar 15, 2016
Grant date	Mar 15, 2016

Abstract

A bootstrap circuit for a sampling transistor. A circuit includes a MOS transistor having a source terminal coupled to an input for receiving an input voltage; an output at a drain terminal of the MOS transistor coupled to one plate of a sampling capacitor; a first switch coupling the input voltage to a gate terminal of the MOS transistor responsive to an initial phase control signal; a bootstrap capacitor having a top plate coupled to the gate terminal of the MOS transistor and coupled to the first switch; a second switch coupling a bottom plate of the bootstrap capacitor to a first low voltage supply responsive to the initial phase control signal; a third switch coupling the bottom plate of the bootstrap capacitor to a positive voltage supply greater than the first low voltage supply responsive to a first phase periodic control signal. Additional circuits and systems are disclosed.

First claim

What is claimed is:

1. A bootstrap circuit for a sampling transistor for a switched capacitor, comprising:
a MOS transistor having a source terminal coupled to an input for receiving an input voltage;
an output at a drain terminal of the MOS transistor coupled to one plate of a sampling capacitor;
a first switch coupling the input voltage to a gate terminal of the MOS transistor responsive to an initial phase control signal;
a bootstrap capacitor having a top plate coupled to the gate terminal of the MOS transistor and coupled to the first switch;
a second switch coupling a bottom plate of the bootstrap capacitor to a first low voltage supply responsive to the initial phase control signal;
a third switch coupling the bottom plate of the bootstrap capacitor to a positive voltage supply greater than the first low voltage supply responsive to a first phase periodic control signal; and
a fourth switch coupling the bottom plate of the bootstrap capacitor to a second low voltage supply lower than the first low voltage supply, responsive to a second phase periodic control signal.

2. The bootstrap circuit of claim 1 , wherein the first switch and the second switch are closed during an initial phase responsive to the initial phase control signal, coupling the top plate of the bootstrap capacitor to the input voltage and charging the bootstrap capacitor to the input voltage.

3. The bootstrap circuit of claim 2 , wherein the third switch is closed during each high portion of the first phase periodic control signal, boosting the gate voltage of the MOS transistor to a voltage that is a sum of the input voltage stored on the bootstrap capacitor and the positive supply voltage.

4. The bootstrap circuit of claim 3 , wherein the fourth switch is closed during each high portion of the second phase periodic control signal, coupling the gate of the MOS transistor to the second low voltage plus the input voltage stored on the bootstrap capacitor.

5. The bootstrap circuit of claim 3 , wherein the input voltage is coupled to the sampling capacitor during each high portion of the first phase periodic control signal by a current conduction path of the MOS transistor, which is turned on by the boosted gate voltage.

6. The bootstrap circuit of claim 1 , wherein the MOS transistor is an N-type MOS transistor.

7. The bootstrap circuit of claim 1 , wherein each of the first, second, third and fourth switches comprise a MOS transistor.

8. The bootstrap circuit of claim 7 , wherein the first, second, third and fourth switches each comprise an N-type MOS transistor.

9. The bootstrap circuit of claim 1 , wherein the initial phase control signal is high only for an initial portion of a sampling cycle, and the first phase periodic control signal and the second phase periodic control signal are repeating periodic signals that continue for a remaining portion of the sampling cycle, the first and the second periodic control signals having similar duty cycles that are non-overlapping.

10. An analog to digital converter integrated circuit, comprising:
a plurality of inputs each configured to receive an analog input signal;
a plurality of resettable delta sigma analog to digital converter stages, each comprising:
a plurality of driver circuits, each coupled to a respective one of the plurality of inputs, each comprising an amplifier and an integrator capacitor and outputting a sampled input voltage;
a plurality of switched capacitor input stages, each coupled to receive at least one of the sampled input voltages at an input, each of the switched capacitor input stages further comprising:
the input receiving the sampled input voltages and coupled to a source terminal of a MOS transistor;
an output at a drain terminal of the MOS transistor coupled to one plate of a sampling capacitor;
a first switch coupling the input to a gate terminal of the MOS transistor, responsive to an initial phase control signal;
a bootstrap capacitor having a top plate coupled to a gate terminal of the MOS transistor and to the first switch;
a second switch coupling a bottom plate of the bootstrap capacitor to a first low voltage supply responsive to the initial phase control signal;
a third switch coupling the bottom plate of the bootstrap capacitor to a positive voltage supply greater than the first low voltage supply responsive to a first phase periodic control signal; and
a fourth switch coupling the bottom plate of the bootstrap capacitor to a second low voltage supply lower than the first low voltage supply, responsive to a second phase periodic control signal.

11. The analog to digital converter circuit of claim 10 , and further comprising: control circuitry coupled to provide the initial phase control signal at an initial portion of a sampling operation, and further coupled in a run portion of the sampling operation to subsequently provide the first phase periodic control signal and the second phase periodic control signal as repeating periodic signals that are non-overlapping.

12. The analog to digital converter circuit of claim 10 , and further comprising a plurality of analog to digital converter stages coupled to respective ones of the sampling capacitors and configured to output digital data corresponding to the analog input signals.

13. The analog to digital converter circuit of claim 10 , wherein the MOS transistors are N-type MOS transistors.

14. The analog to digital converter circuits of claim 10 , wherein during a high portion of the first phase periodic control signal, the voltage input at the source of the MOS transistors is coupled to the drain of the MOS transistors and to the sampling capacitor, due to the gate to source voltage of the MOS transistors which is boosted by the bootstrap capacitor to the positive supply voltage.

15. A system for imaging, comprising:
an apparatus for creating images comprising a plurality of radiation emitters spaced from and directed towards a plurality of photo-detectors sensitive to the emitted radiation, the plurality of photo-detectors outputting analog output signals corresponding to an intensity of the radiation received at the photo-detectors;
at least one analog-to-digital converter integrated circuit having a plurality of inputs coupled to receive analog output signals from the plurality of photo-detectors, and further comprising:
a plurality of analog to digital converter stages including an analog-to-digital converter stage configured to output digital data corresponding to the analog output signals, each of the analog to digital converter stages comprising:
a plurality of driver circuits, each coupled to a respective one of the plurality of inputs, each comprising an amplifier and a capacitor coupled to sample an analog signal and each outputting a corresponding input voltage;
a plurality of switched capacitor input stages, each coupled to the output of at least one of the driver circuits, each of the switched capacitor input stages further comprising:
a MOS sampling transistor having a current conduction path coupled between the input voltage and an output, and having a gate terminal;
one plate of a sampling capacitor coupled to the output of the MOS sampling transistor;
a first switch coupling the input voltage to the gate terminal of the MOS sampling transistor, responsive to an initial phase control signal;
a bootstrap capacitor having a top plate coupled to the gate terminal of the MOS sampling transistor and to the first switch;
a second switch coupling a bottom plate of the bootstrap capacitor to a first low voltage supply responsive to the initial phase control signal;
a third switch

Assignees

• Texas Instruments Inc

Inventors

• Viswanath Rakul
• Sharma Rahul

Classifications

• H03M3/496

  Details of sampling arrangements or methods · CPC title

• H03K17/063 Primary

  in field-effect transistor switches · CPC title

• H03K17/16

  Modifications for eliminating interference voltages or currents · CPC title

• G01N23/046

  using tomography, e.g. computed tomography [CT] · CPC title

• H03K2217/0036

  Means reducing energy consumption · CPC title