Managing memory maintenance operations in a memory system having backing storage media

Patent metadata

Field	Value
Publication number	US-12147345-B2
Application number	US-202218074217-A
Country	US
Kind code	B2
Filing date	Dec 2, 2022
Priority date	May 13, 2019
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory system is disclosed. The memory system includes volatile memory configured as a cache. The cache stores first data at first storage locations. Backing storage media couples to the cache. The backing storage media stores second data in second storage locations corresponding to the first data. Logic uses a presence or status of first data in the first storage locations to cease maintenance operations to the stored second data in the second storage locations.

First claim

We claim:

1. A memory, comprising:
cache memory to store first data;
backing storage media coupled to the cache memory, the backing storage media to store second data corresponding to the first data in a hierarchical relationship; and
buffer circuitry coupled to the cache memory and the backing store media to cease maintaining the correspondence of the second data to the first data when a status of the first data indicates that the first data no longer corresponds to the second data.

2. The memory of claim 1 , wherein:
the first data is stored in a first page of volatile memory storage cells; and
the second data is stored in a second page of storage class memory (SCM) storage cells.

3. The memory of claim 2 , wherein:
the volatile memory storage cells comprise dynamic random access memory (DRAM).

4. The memory of claim 2 , wherein:
the SCM storage cells comprise non-volatile memory cells.

5. The memory of claim 4 , wherein:
the non-volatile memory cells comprise flash memory cells.

6. The memory of claim 1 , wherein the buffer circuitry further comprises:
a cache manager circuit to manage operations directed to the cache memory; and
a backing store media manager circuit to manage the backing store media.

7. The memory of claim 6 , further comprising:
storage configured as a lookup table to store page allocation information identifying managed/unmanaged backing store pages corresponding to the status of the first data stored in the cache.

8. The memory of claim 1 , wherein the buffer circuit further comprises:
an interface to receive commands generated by an external host, the commands specifying page-related status information for the first data in the cache memory.

9. A memory module, comprising:
a substrate;
a memory sub-system including
cache memory to store first data;
backing storage media coupled to the cache memory, the backing storage media to store second data corresponding to the first data; and
buffer circuitry to selectively cease maintaining the correspondence of the second data to the first data when a status of the first data indicates that the first data no longer corresponds to the second data.

10. The memory module of claim 9 , wherein:
the backing storage media comprises multiple flash memory devices.

11. The memory module of claim 9 , wherein the buffer circuitry further comprises:
a cache manager circuit to manage operations directed to the cache memory; and
a backing storage media manager circuit to manage the backing storage media.

12. The memory module of claim 11 , further comprising:
storage configured as a lookup table to store page allocation information identifying managed/unmanaged backing store pages corresponding to the status of the first data stored in the cache.

13. The memory module of claim 9 , wherein the buffer circuitry further comprises:
an interface to receive commands generated external to the memory module, the commands specifying page-related status information for the first data in the cache memory.

14. The memory module of claim 13 , wherein:
the page-related status information includes at least one from the group comprising data unallocation, data load and unallocation, and data read-only.

15. A method of operation in a memory system, the method comprising:
storing first data at first volatile memory storage locations in a cache memory;
selectively storing a copy of the first data as stored second data in a second location of a backing storage media for the cache memory, and
ceasing maintaining the correspondence of the second data to the first data when a status of the first data indicates that the first data no longer corresponds to the second data.

16. The method of claim 15 , wherein:
the selectively maintaining the copy of the second data with respect to the first data is controlled locally on a memory module by buffer circuitry, the cache memory, the buffer circuitry and the backing storage media disposed on the memory module.

17. The method of claim 16 , wherein the buffer circuitry includes a backing storage media memory manager circuit, and wherein the method further comprises:
detecting changes to data status of pages in the cache memory with the backing storage media memory manager circuit.

18. The method of claim 16 , wherein:
the selectively maintaining the copy of the second data with respect to the first data is controlled by the buffer circuitry in response to commands generated remotely by a system controller host.

Assignees

• Rambus Inc

Inventors

• Williams Collins
• Miller Michael
• Wright Kenneth

Classifications

• G11C14/0018

  whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F2212/283

  Plural cache memories · CPC title

• G06F2212/313

  In storage device · CPC title