Memory persistence management control

Patent metadata

Field	Value
Publication number	US-2016155491-A1
Application number	US-201414555639-A
Country	US
Kind code	A1
Filing date	Nov 27, 2014
Priority date	Nov 27, 2014
Publication date	Jun 2, 2016
Grant date	—

Abstract

A memory retention controller may include a data structure configured to store a memory refresh interval corresponding to a memory region in a memory subsystem and control logic coupled with the data structure. The control logic is configured to perform a first refresh of the memory region prior to a power off transition of a host processor coupled with the memory subsystem, and to perform a second refresh of the memory region after the power off transition of the host processor, based on the memory refresh interval corresponding to the memory region, and in response to an elapsed time since the first refresh of the memory region.

First claim

What is claimed is:

1 . A memory retention controller, comprising:
a data structure configured to store a memory refresh interval corresponding to a memory region in a memory subsystem; and control logic coupled with the data structure and configured to
perform a first refresh of the memory region prior to a power off transition of a host processor coupled with the memory subsystem, and
perform a second refresh of the memory region after the power off transition of the host processor, based on the memory refresh interval corresponding to the memory region, and in response to an elapsed time since the first refresh of the memory region.

2 . The memory retention controller of claim 1 , wherein the data structure stores a next refresh time for the memory region, and wherein the control logic is configured to perform the second refresh at a time indicated by the next refresh time.

3 . The memory retention controller of claim 1 , wherein the control logic comprises refresh logic configured to perform the first refresh and the second refresh, wherein the first refresh and the second refresh are of a series of memory refreshes performed at a first frequency indicated by the memory refresh interval corresponding to the memory region.

4 . The memory retention controller of claim 3 , wherein the control logic is further configured to:
change the stored memory refresh interval in response to a detected environmental condition; and in response to a change of the stored memory refresh interval to a new memory refresh interval, perform the series of memory refreshes at a second frequency indicated by the new memory refresh interval.

5 . The memory retention controller of claim 4 , further comprising a temperature sensor coupled with the control logic, wherein the detected environmental condition is an increase in temperature detected by the temperature sensor, and wherein the increase in the temperature corresponds to a new memory refresh interval that is shorter than the stored memory refresh interval.

6 . The memory retention controller of claim 4 , further comprising a cache memory coupled with the control logic and configured to store the data structure, wherein the control logic is further configured to, if the memory refresh interval is greater than the new memory refresh interval, store the new memory refresh interval by a write-through operation to the cache memory and a backing store of the cache memory.

7 . The memory retention controller of claim 1 , wherein a first clock signal coupled with the control logic has a lower frequency than a second clock signal coupled with the host processor, and wherein the control logic comprises near-threshold logic.

8 . The memory retention controller of claim 1 , wherein the control logic is further configured to initiate at least one of a plurality of memory maintenance operations on the memory region, wherein the plurality of memory maintenance operations comprises a memory scrubbing operation and a data migration operation.

9 . The memory retention controller of claim 8 , wherein control logic is configured to:
initiate a power on transition of the host processor; and cause the host processor to perform the one or more memory maintenance operations on the memory region.

10 . A method, comprising:
storing in a data structure a memory refresh interval corresponding to a memory region in a memory subsystem; performing a first refresh of the memory region prior to a power off transition of a host processor coupled with the memory subsystem; and performing a second refresh of the memory region after the power off transition of the host processor, based on the memory refresh interval corresponding to the memory region, and in response to an elapsed time since the first refresh of the memory region.

11 . The method of claim 10 , further comprising performing a series of memory refreshes at a first frequency indicated by the memory refresh interval corresponding to the memory region, wherein the series of memory refreshes includes the first refresh and the second refresh.

12 . The method of claim 11 , further comprising, in response to a change of the stored memory refresh interval to a new memory refresh interval, performing the series of memory refreshes at a second frequency indicated by the new memory refresh interval.

13 . The method of claim 12 , further comprising:
storing the data structure in a cache memory; and if the memory refresh interval is greater than the new memory refresh interval, storing the new memory refresh interval by a write-through operation to the cache memory and a backing store of the cache memory.

14 . The method of claim 10 , further comprising:
initiating a power on transition of the host processor; and causing the host processor to perform the one or more memory maintenance operations on the memory region.

15 . A computing system, comprising:
a host processor; a memory subsystem coupled with the host processor; and a memory retention controller coupled with the memory subsystem, the memory retention controller comprising:
a data structure configured to store a memory refresh interval corresponding to a memory region in the memory subsystem, and
control logic coupled with the data structure and configured to
perform a first refresh of the memory region prior to a power off transition of the host processor, and
perform a second refresh of the memory region after the power off transition of the host processor, based on the memory refresh interval corresponding to the memory region, and in response to an elapsed time since the first refresh of the memory region.

16 . The computing system of claim 15 , further comprising an auxiliary power supply coupled with the memory retention controller and configured to supply power to the memory retention controller when the host processor is in a powered off state.

17 . The computing system of claim 16 , wherein control logic is further configured to:
initiate a power on transition of the host processor; and cause the host processor to perform the one or more memory maintenance operations on the memory region.

18 . The computing system of claim 15 , further comprising a plurality of slave retention controllers including the memory retention controller, wherein each of the plurality of slave retention controllers is coupled with a master retention controller and stores one or more memory refresh intervals corresponding respectively to one or more memory regions of the memory subsystem.

19 . The computing system of claim 18 , wherein each slave retention controller of the plurality of slave retention controllers is configured to:
cause the master retention controller to transition from a lower power consumption state to a higher power consumption state; and cause the master retention controller to initiate one or more memory maintenance operations on the memory region corresponding to the slave retention controller.

20 . The computing system of claim 15 , wherein the memory retention controller is located on a logic die in a memory stack, and wherein the memory region is located on one or more memory dies in the memory stack.

Assignees

• Advanced Micro Devices Inc

Inventors

• Roberts David A
• Ignatowski Michael

Classifications

• G11C11/40626

  Temperature related aspects of refresh operations · CPC title

• G11C11/40607 Primary

  Refresh operations in memory devices with an internal cache or data buffer · CPC title

• G11C2211/4068

  Voltage or leakage in refresh operations · CPC title

• G11C11/40611

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G11C2211/4067

  Refresh in standby or low power modes · CPC title