Printed circuit board and camera device comprising same

US12144103B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12144103-B2
Application numberUS-201917252172-A
CountryUS
Kind codeB2
Filing dateJun 14, 2019
Priority dateJun 15, 2018
Publication dateNov 12, 2024
Grant dateNov 12, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A printed circuit board according to an embodiment comprises: a substrate comprising at least two insulating layers; pads arranged on the substrate; heat dissipation vias arranged to pass through the substrate in a region of the substrate which vertically overlaps the pads; and through vias arranged to pass through the substrate in a region of the substrate which does not vertically overlap the pads, wherein each heat dissipation via includes a plurality of via parts which are spaced apart from each other in at least one of the at least two insulating layers, the upper surface of each of the plurality of via parts has a first horizontal width in a first direction that is smaller than a second horizontal width thereof in a second direction different from the first direction, and the plurality of via parts have a surface area corresponding to 10% or greater of the surface area of the pads.

First claim

Opening claim text (preview).

The invention claimed is: 1. A circuit board comprising: a substrate; a heat dissipation via passing through at least a portion of the substrate; a through via passing through a portion of the substrate and spaced apart from the heat dissipation via in a horizontal direction; a pad disposed on the substrate and overlapping with the heat dissipation via in a vertical direction and not overlapping with the through via in the vertical direction; a first connection part disposed on the pad; a first element mounted on the first connection part, a second connection part disposed on the pad and spaced apart from the first connection part in the horizontal direction; and a second element mounted on the second connection part, wherein the first element includes a first region overlapping the pad in the vertical direction and a second region non-overlapping with the pad in the vertical direction, wherein a part of the second region of the first element overlaps the through via in the vertical direction, wherein the pad includes an overlap region overlapping the heat dissipation via in the vertical direction and a non-overlapping region not overlapping with the heat dissipation via in the vertical direction, and wherein the first and second connection parts are disposed on the non-overlapping region of the pad. 2. The circuit board of claim 1 , wherein an entire region of the second element is overlapped with the pad in the vertical direction. 3. The circuit board of claim 1 , wherein the second region does not overlap the heat dissipation via. 4. The circuit board of claim 1 , wherein the heat dissipation via comprises a plurality of heat dissipation via parts spaced apart from each other in the horizontal direction, and wherein the plurality of heat dissipation via parts are commonly connected to the pad. 5. The circuit board of claim 4 , wherein each of the plurality of heat dissipation via parts has a first width smaller in a first horizontal direction than a second width in a second horizontal direction different from the first horizontal direction. 6. The circuit board of claim 4 , wherein the plurality of heat dissipation via parts have a surface area of 10% or more of a surface area of the pad. 7. The circuit board of claim 5 , wherein widths of the through via in the first and second horizontal directions are smaller than the second width. 8. The circuit board of claim 1 , wherein the substrate comprises a first insulating layer and a second insulating layer, wherein the heat dissipation via includes a first heat dissipation via passing through the first insulating layer, and a second heat dissipation via passing through the second insulating layer, and wherein the first heat dissipation via overlaps the second heat dissipation via in the vertical direction. 9. The circuit board of claim 2 , wherein the first element includes a driver element; and wherein the second element includes a vertical cavity type surface-emission laser element. 10. The circuit board of claim 2 , wherein the first element comprises a ground terminal overlapping the first connection part in the vertical direction, and wherein the ground terminal is connected to the second element through the pad. 11. The circuit board of claim 9 , wherein the second element includes a cathode electrode, wherein the second connection part is disposed between the cathode electrode and the pad, and wherein the cathode electrode and a ground terminal are connected to each other through the pad. 12. The circuit board of claim 11 , wherein an upper surface of the overlap region of the pad includes a concave portion provided in a region overlapping the heat dissipation via in the vertical direction.

Assignees

Inventors

Classifications

  • comprising multiple insulating layers · CPC title

  • of vias therein · CPC title

  • H10W40/228Primary

    the projecting parts being wire-shaped or pin-shaped · CPC title

  • directly combined with via connections · CPC title

  • Passive cooling, e.g. where heat is removed by the housing as a whole or by a heat pipe without any active cooling element like a TEC · CPC title

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Frequently asked questions

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What does patent US12144103B2 cover?
A printed circuit board according to an embodiment comprises: a substrate comprising at least two insulating layers; pads arranged on the substrate; heat dissipation vias arranged to pass through the substrate in a region of the substrate which vertically overlaps the pads; and through vias arranged to pass through the substrate in a region of the substrate which does not vertically overlap the…
Who is the assignee on this patent?
Lg Innotek Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W40/228. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 12 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).