Semiconductor packages with optical interconnection structures, memory cards including the same, and electronic systems including the same

Patent metadata

Field	Value
Publication number	US-2016142155-A1
Application number	US-201514704174-A
Country	US
Kind code	A1
Filing date	May 5, 2015
Priority date	Nov 17, 2014
Publication date	May 19, 2016
Grant date	—

Abstract

A semiconductor package includes a first transceiver disposed on a top surface of a substrate; and a second transceiver disposed on a bottom surface of the substrate. The first and second transceivers optically communicate with each other through optical signals that permeate the substrate.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a semiconductor chip disposed on a top surface of an interposer; a first driver chip and a second driver chip disposed on the top surface and a bottom surface of the interposer respectively; a first optical transmitter and a first optical receiver mounted on a surface of the first driver chip and controlled by the first driver chip; and a second optical transmitter and a second optical receiver mounted on a surface of the second driver chip and controlled by the second driver chip, wherein the second optical transmitter and the second optical receiver optically communicate with the first optical transmitter and the first optical receiver through optical signals that permeate the interposer.

2 . The semiconductor package of claim 1 , wherein the first and second driver chips are disposed to overlap with a portion of the interposer to face each other.

3 . The semiconductor package of claim 2 , wherein the first optical transmitter and the first optical receiver are mounted on a surface of the first driver chip that faces the second driver chip.

4 . The semiconductor package of claim 3 ,
wherein the second optical receiver is mounted on a surface of the second driver chip that faces the first driver chip and is aligned with the first optical transmitter so that a first optical signal generated from the first optical transmitter permeates the interposer to reach the second optical receiver; and wherein the second optical transmitter is mounted on a surface of the second driver chip that faces the first driver chip and is aligned with the first optical receiver so that a second optical signal generated from the second optical transmitter permeates the interposer to reach the first optical receiver.

5 . The semiconductor package of claim 4 , wherein the interposer includes a transparent light permeation portion through which the first and second optical signals pass.

6 . The semiconductor package of claim 4 , wherein the interposer includes a silicon material wherein the first and second optical signals pass.

7 . The semiconductor package of claim 6 , wherein the first and second optical signals are infrared (IR) rays.

8 . The semiconductor package of claim 7 , wherein the first and second optical signals have a wavelength of 1200 nanometers to 15000 nanometers.

9 . The semiconductor package of claim 4 , wherein the first and second optical signals are transmitted via through holes that penetrate the interposer.

10 . The semiconductor package of claim 1 , wherein the semiconductor chip includes a memory chip, a central processing unit (CPU) chip, a system large-scale integration (LSI) chip, or a field programmable gate array (FPGA) chip.

11 . The semiconductor package of claim 1 , wherein the first optical transmitter includes a laser device and the first optical receiver includes a photo detector.

12 . The semiconductor package of claim 11 ,
wherein the first driver chip controls the laser device so that the laser device converts an electrical signal outputted from the semiconductor chip into one of the optical signals; or wherein the first driver chip controls the photo detector to convert the another one of the optical signals into an electrical signal and to transmit the electrical signal to the semiconductor chip.

13 . The semiconductor package of claim 1 , further comprising:
a first conductive interconnection line for electrically coupling the semiconductor chip to the first driver chip; a signal terminal disposed on the bottom surface of the interposer; and a second conductive interconnection line for electrically coupling the second driver chip to the signal terminal.

14 . The semiconductor package of claim 13 , further comprising:
a first through via penetrating the interposer; and a third conductive interconnection line disposed on the top surface of the interposer to electrically couple one end of the first through via to the first driver chip.

15 . The semiconductor package of claim 14 , further comprising:
a power supply terminal disposed on the bottom surface of the interposer and electrically coupled to an other end of the first through via.

16 . The semiconductor package of claim 15 , further comprising:
a fourth conductive interconnection line disposed on the bottom surface of the interposer to electrically couple the power supply terminal to the second driver chip.

17 . The semiconductor package of claim 14 , further comprising:
another signal terminal disposed on the bottom surface of the interposer and electrically coupled to the other end of the first through via.

18 . The semiconductor package of claim 16 , further comprising:
a second through via penetrating the interposer; and a fifth conductive interconnection line disposed on the top surface of the interposer to electrically couple one end of the second through via to the semiconductor chip.

19 . A semiconductor package comprising:
a first driver chip and a second driver chip respectively disposed on a top surface and a bottom surface of the interposer respectively; a first semiconductor chip disposed on the top surface of the interposer and electrically coupled to the first driver chip; a second semiconductor chip disposed on the bottom surface of the interposer and electrically coupled to the second driver chip; first conductive interconnection lines for electrically coupling the first semiconductor chip to the first driver chip; sixth conductive interconnection lines for electrically coupling the second semiconductor chip to the second driver chip; a first optical transmitter and a first optical receiver mounted on a surface of the first driver chip and controlled by the first driver chip; a second optical transmitter and a second optical receiver mounted on a surface of the second driver chip and controlled by the second driver chip; a signal terminal disposed on the bottom surface of the interposer; and a second conductive interconnection line for electrically coupling the second driver chip to the signal terminal, wherein the second optical transmitter and the second optical receiver optically communicate with the first optical transmitter and the first optical receiver through optical signals permeating the interposer.

20 . A semiconductor package comprising:
a first transceiver disposed on a top surface of a substrate; and a second transceiver disposed on a bottom surface of the substrate, wherein the first and second transceivers optically communicate with each other through optical signals that permeate the substrate.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jong Hoon

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H04B10/40

  Transceivers · CPC title

• H04B10/803 Primary

  Free space interconnects, e.g. between circuit boards or chips · CPC title

• H04B10/501

  Structural aspects · CPC title

• H04B10/801 Primary

  using optical interconnects, e.g. light coupled isolators, circuit board interconnections · CPC title