Semiconductor package and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9984950-B2
Application number	US-201715441188-A
Country	US
Kind code	B2
Filing date	Feb 23, 2017
Priority date	Apr 20, 2016
Publication date	May 29, 2018
Grant date	May 29, 2018

Abstract

Disclosed is a semiconductor package including: a base substrate provided with at least one cavity and made of a metallic material; at least one semiconductor chip mounted in the cavity; and a heat dissipating member arranged in a gap between an inner surface of the cavity and the semiconductor chip.

First claim

What is claimed is:

1. A semiconductor package comprising:
a base substrate provided with at least one cavity and made of a metallic material;
at least one semiconductor chip mounted in the cavity;
a heat dissipating member arranged in a gap between an inner surface of the cavity and the semiconductor chip, wherein the heat dissipating member covers a back surface and side surfaces of the semiconductor chip, and covers a back surface of the base substrate; and
at least one trench extending through the base substrate and the heat dissipating member in a thickness direction thereof, thereby dividing the base substrate and the heat dissipating member into a ground portion and an electrode portion and electrically insulating the ground portion and the electrode portion from each other.

2. The semiconductor package according to claim 1 , further comprising at least one electrode pattern formed on a front surface of the base substrate and electrically connected to the base substrate.

3. The semiconductor package according to claim 1 , wherein the ground portion includes a first base substrate within which the semiconductor chip is mounted and a first heat dissipating member covering the back surface of the first base substrate, and wherein the electrode portion includes a second base substrate electrically insulated from the first base substrate and a heat dissipating member covering the back surface of the second base substrate.

4. The semiconductor package according to claim 3 , wherein the trench includes a first portion extending in a first direction of a surface of the base substrate and having a predetermined length and a second portion extending from an end of the first portion in a second direction different from the first direction and having a predetermined length.

5. The semiconductor package according to claim 4 , wherein the electrode portion is formed near an edge of the base substrate and wherein the electrode portion and an electrode pad of the semiconductor chip are formed in one-on-one correspondence.

6. The semiconductor package according to claim 5 , wherein the trench is formed such that the first portion extends in a widthwise direction of the base substrate and having the predetermined length and the second portion extends from the end of the first portion in a lengthwise direction of the base substrate and having the predetermined length, separating the electrode portion from the ground portion by a predetermined distance.

7. A method for manufacturing a semiconductor package, the method comprising:
forming at least one cavity in a base substrate made of a metallic material;
mounting a semiconductor chip in the cavity;
forming a heat dissipating member to fill a gap between an inner surface of the cavity and the semiconductor chip and to cover a back surface of the base substrate; and
dividing the base substrate and the heat dissipating member into a ground portion within which the semiconductor is mounted and an electrode portion electrically insulated from and located on one side of the ground portion.

8. The method according to claim 7 , further comprising:
forming an insulation layer on a front surface of the base substrate after the forming of the heat dissipating member; and
forming an electrode pattern electrically connected to the semiconductor chip and an electrode pattern electrically connected to a portion of the base substrate, on the insulation layer.

9. The method according to claim 7 , wherein the dividing of the base substrate and the heat dissipating member includes:
forming at least one trench at a boundary portion between the ground portion and the electrode portion, thereby separating the ground portion from the electrode portion by a predetermined distance, the trench extending through the base substrate and the heat dissipating member in a thickness direction and being elongated in a longitudinal direction and a widthwise direction of the base substrate when shown in a plan view of the base substrate;
filling the trench with an insulation material and forming an insulation layer on the front surface of the base substrate;
forming an electrode pattern that electrically connects an electrode pad of the semiconductor chip to the electrode portion; and
cutting the base substrate and the heat dissipating member along dicing lines extending at positions near respective ends of the trench, thereby electrically insulating the ground portion and the electrode portion from each other.

Assignees

• Korea Electronics Technology

Inventors

• Kim Jun Chul
• Kim Dong Su
• Yook Jong Min

Classifications

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H10W74/01

  Manufacture or treatment · CPC title

• H10W72/071

  Connecting or disconnecting · CPC title