Field effect transistor

Patent metadata

Field	Value
Publication number	US-12142686-B2
Application number	US-202117330780-A
Country	US
Kind code	B2
Filing date	May 26, 2021
Priority date	May 26, 2021
Publication date	Nov 12, 2024
Grant date	Nov 12, 2024

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to field effect transistors and methods of manufacture. The structure includes: at least one gate structure having source/drain regions; at least one isolation structure within the source/drain regions in a substrate material; and semiconductor material on a surface of the at least one isolation structure in the source/drain regions.

First claim

What is claimed:

1. A structure comprising:
at least one gate structure and accompanying source/drain regions;
isolation structures under the source/drain regions and partially under the at least one gate structure, and upper surfaces of a substrate material and the isolation structures are planar; and
semiconductor material on a surface of the at least one isolation structure of the isolation structures which comprises the source/drain regions and on an upper surface of the substrate material, wherein:
the semiconductor material extends onto and in direct contact with the upper surface of the substrate material adjacent to the isolation structure under the at least one gate structure;
the at least one gate structure includes two gate structures;
a first gate structure of the gate structures extends over and is in direct contact with a first isolation structure of the isolation structures;
the source/drain regions is directly in contact with a second isolation structure of the isolation structures, between the two gate structures;
a silicide is provided on the source/drain regions between the two gate structures; and
the second gate structure is on and contacts the semiconductor material on the upper surface of the substrate material.

2. The structure of claim 1 , wherein the semiconductor material comprises crystalline Si material on the substrate material and polysilicon material on the isolation structures.

3. The structure of claim 2 , wherein the at least one gate structure is located over the crystalline Si material.

4. The structure of claim 2 , wherein the at least one gate structure comprises a multi-finger gate structure with a plurality of fingers over the crystalline Si material.

5. The structure of claim 2 , wherein the crystalline Si material partially overlaps onto a surface of the isolation structures.

6. The structure of claim 2 , wherein sidewalls spacers of the at least one gate structure are at a junction of the polysilicon material and the crystalline Si material.

7. The structure of claim 2 , further comprising silicide covering the polysilicon material and over the at least one gate structure, and contacts connecting to the silicide in the source/drain regions and over the at least one gate structure.

8. The structure of claim 2 , wherein the polysilicon material includes a break on at least one of the isolation structures.

9. The structure of claim 1 , wherein the semiconductor material comprises crystalline Si material on the substrate material and polysilicon on the isolation structures.

10. The structure of claim 9 , wherein the crystalline Si material is a discontinuous layer.

11. The structure of claim 1 , further comprising a silicide on the semiconductor material of the source/drain regions and over the at least one gate structure, and an interconnect contact on the silicide in the source/drain regions and the at least one gate structure.

12. The structure of claim 1 , further comprising a high resistivity layer within a semiconductor substrate, below the isolation structures.

13. A structure comprising:
a semiconductor substrate;
a gate structure and accompanying source/drain regions over the semiconductor substrate;
at least one shallow trench isolation structure within the semiconductor substrate and under the source/drain regions of the gate structure and the gate structure, and upper surfaces of the semiconductor substrate and the at least one shallow trench isolation structure being planar;
semiconductor material over the at least one shallow trench isolation structure and the upper surface of the semiconductor substrate, and under the gate structure, the semiconductor material comprising the source/drain regions over the semiconductor substrate;
a second gate structure with accompanying source drain regions over the semiconductor substrate, the second gate structure being over the semiconductor material and adjacent to the at least one shallow trench isolation structure; and
silicide on the semiconductor material over the at least one shallow trench isolation structure, wherein:
the semiconductor material over the at least one shallow trench isolation structure comprises polysilicon material and the semiconductor material under the gate structure comprises crystalline Si material;
the gate structure extends over and is in direct contact with a first shallow trench isolation structure of the at least one shallow trench isolation structure;
the source/drain region of the gate structure is directly in contact with a second shallow trench isolation structure of the at least one shallow trench isolation structure, between the gate structure and the second gate structure; and
the second gate structure is on and directly contacts the semiconductor material which directly contacts the upper surface of the semiconductor substrate.

14. The structure of claim 13 , wherein the polysilicon material is separated from the gate structure by the crystalline Si material.

15. The structure of claim 14 , further comprising an interconnect structure connecting to the silicide in the source/drain regions of the gate structure.

16. The structure of claim 14 , wherein the polysilicon material is a discontinuous layer and is provided on at least a portion of the at least one shallow trench isolation structure.

17. The structure of claim 13 , wherein the semiconductor material over the at least one shallow trench isolation structure and under the gate structure comprises crystalline Si material.

18. A method comprising:
forming at least one gate structure and accompanying source/drain regions;
forming isolation structures under the source/drain regions and partially under the at least one gate structure, and also in a substrate material, and upper surfaces of the substrate material and isolation structures are planar; and
forming semiconductor material on a surface of the at least one isolation structure of the isolation structures which comprises the source/drain regions and on an upper surface of the substrate material, wherein:
the semiconductor material extends onto and in direct contact with the upper surface of the substrate material adjacent to the isolation structure under the at least one gate structure;
the at least one gate structure includes two gate structures;
a first gate structure of the gate structures extends over and is in direct contact with a first isolation structure of the isolation structures;
the source/drain regions is directly in contact with a second isolation structure of the isolation structures, between the two gate structures;
a silicide is provided on the source/drain regions between the two gate structures; and
the second gate structure is on and contacts the semiconductor material on the upper surface of the substrate material.

Assignees

• Globalfoundries Us Inc

Inventors

• Stamper Anthony K
• Rana Uzma
• Shank Steven M
• Levy Mark D

Classifications

• H10D62/116 Primary

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D30/6733

  Multi-gate TFTs · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10D30/6744

  Monocrystalline silicon · CPC title

• H10D30/0323

  comprising monocrystalline silicon · CPC title