Integrated circuit having a hidden shared contact

Patent metadata

Field	Value
Publication number	US-10763213-B2
Application number	US-201816037595-A
Country	US
Kind code	B2
Filing date	Jul 17, 2018
Priority date	Jul 21, 2017
Publication date	Sep 1, 2020
Grant date	Sep 1, 2020

Abstract

An integrated circuit includes a substrate and an interconnect. A substrate zone is delineated by an insulating zone. A polysilicon region extends on the insulating zone and includes a strip part. An isolating region is situated between the substrate and the interconnect and covers the substrate zone and the polysilicon region. A first electrically conductive pad passes through the isolating region and has a first end in electrical contact with both the strip part and the substrate zone. A second end of the electrically conductive pad is in electrical contact with the interconnect. A second electrically conductive pad also passes through the isolating region to make electrical contact with another region. The first and second electrically conductive pads have equal or substantially equal cross sectional sizes, within a tolerance.

First claim

The invention claimed is:

1. An integrated circuit, comprising:
a semiconductor substrate including at least one substrate zone delineated by an insulating zone;
a polysilicon region having at least one part situated on said insulating zone, said at least one part of the polysilicon region having a side edge and, at a base of the at least one part, a strip extending perpendicularly away from the side edge above the insulating zone in a direction of said at least one substrate zone;
an interconnection part;
an isolating region situated between the substrate and said interconnection part and covering said at least one substrate zone and said polysilicon region; and
an electrically conductive pad passing through said isolating region and having a first end in electrical contact with both a portion of the strip and a part of said at least one substrate zone and a second end in electrical contact with said interconnection part,
wherein said portion of the strip has a metal silicide.

2. The integrated circuit according to claim 1 , wherein the first end of the electrically conductive pad has a first zone in contact with said portion of the strip, a second zone in contact with said substrate zone, and further including a protrusion extending between the first zone and the second zone.

3. The integrated circuit according to claim 1 , further comprising a plurality of additional contact pads passing through said isolating region and coming into contact with a plurality of substrate zones and component zones of the integrated circuit, wherein cross sections of the plurality of additional contact pads and a cross section of said electrically conductive pad between the first end and the second end are identical or substantially identical, to within a tolerance.

4. An integrated circuit comprising:
a semiconductor substrate including at least one substrate zone delineated by an insulating zone;
a polysilicon region having at least one part situated on said insulating zone, said at least one part of the polysilicon region having a side edge and, at a base of the at least one part, a strip extending perpendicularly away from the side edge above the insulating zone in a direction of said at least one substrate zone;
an interconnection part;
an isolating region situated between the substrate and said interconnection part and covering said at least one substrate zone and said polysilicon region;
an electrically conductive pad passing through said isolating region and having a first end in electrical contact with both a portion of the strip and a part of said at least one substrate zone and a second end in electrical contact with said interconnection part; and
at least one MOS transistor produced on and in an active zone delineated by the insulating region, said active zone having a source region and a drain region, and said substrate zone being one of the source and drain regions.

5. The integrated circuit according to claim 4 , wherein said at least one MOS transistor includes a further polysilicon region forming a first gate region, said polysilicon region forming part of a second gate region of another MOS transistor, wherein a combined width of the at least one part and said strip exceeds a width of the further polysilicon region.

6. The integrated circuit according to claim 4 , wherein the first end of the electrically conductive pad has a first zone in contact with said portion of the strip, a second zone in contact with said substrate zone, and further including a protrusion extending between the first zone and the second zone.

7. The integrated circuit according to claim 4 , further comprising a plurality of additional contact pads passing through said isolating region and coming into contact with a plurality of substrate zones and component zones of the integrated circuit, wherein cross sections of the plurality of additional contact pads and a cross section of said electrically conductive pad between the first end and the second end are identical or substantially identical, to within a tolerance.

8. An integrated circuit, comprising:
a semiconductor substrate including at least one substrate zone delineated by an insulating zone;
a polysilicon region having at least one part situated on said insulating zone, said at least one part of the polysilicon region having a side edge and, at a base of the at least one part, a strip extending perpendicularly away from the side edge above the insulating zone in a direction of said at least one substrate zone;
an interconnection part;
an isolating region situated between the substrate and said interconnection part and covering said at least one substrate zone and said polysilicon region; and
an electrically conductive pad passing through said isolating region and having a first end in electrical contact with both a portion of the strip and a part of said at least one substrate zone and a second end in electrical contact with said interconnection part;
wherein said polysilicon region is a part of a gate region of another transistor.

9. The integrated circuit according to claim 8 , wherein an insulating gate sidewall spacer is provided on said edge of said at least one part of the polysilicon region, but no insulating gate sidewall spacer is provided on a side edge of the strip.

10. The integrated circuit according to claim 8 , wherein the first end of the electrically conductive pad has a first zone in contact with said portion of the strip, a second zone in contact with said substrate zone, and further including a protrusion extending between the first zone and the second zone.

11. The integrated circuit according to claim 8 , further comprising a plurality of additional contact pads passing through said isolating region and coming into contact with a plurality of substrate zones and component zones of the integrated circuit, wherein cross sections of the plurality of additional contact pads and a cross section of said electrically conductive pad between the first end and the second end are identical or substantially identical, to within a tolerance.

12. A method for producing, within an integrated circuit, at least one shared electrically conductive contact pad between a substrate zone situated in a semiconductor substrate of the integrated circuit and delineated by an insulating zone, and a polysilicon region having at least one part situated on said insulating zone, the method comprising:
forming said polysilicon region by forming, at a base of said at least one part of the polysilicon region, a strip extending perpendicularly away from a side edge of said at least one part and above the insulating zone in the direction of said substrate zone;
forming an isolating region situated above the semiconductor substrate and covering said substrate zone and said polysilicon region;
forming said at least one shared electrically conductive contact pad passing through said isolating region and having a first end in electrical contact with both a portion of the strip and a part of said at least one substrate zone and having a second end; and
forming an interconnection region of the integrated circuit in electrical contact with said second end of said at least one shared electrically conductive contact pad; and
siliciding said portion of the strip.

13. The method according to claim 12 , comprising simultaneously forming said at least one shared electrically conductive contact pad and a plurality of additional contact pads passing through said isolating region and coming into contact with a plurality of substrate zones and component zones of the integrated circuit, wherein simultaneously forming comprises using a single c

Assignees

• St Microelectronics Rousset

Inventors

• Delalleau Julien
• Rivero Christian

Classifications

• H10D64/01306

  the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon · CPC title

• H10W20/0698 Primary

  Local interconnections · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title