Transistor

Patent metadata

Field	Value
Publication number	US-9748383-B2
Application number	US-86725709-A
Country	US
Kind code	B2
Filing date	Feb 12, 2009
Priority date	Feb 15, 2008
Publication date	Aug 29, 2017
Grant date	Aug 29, 2017

Abstract

A Metal Oxide Semiconductor (MOS) transistor comprising: a source; a gate; and a drain, the source, gate and drain being located in or on a well structure of a first doping polarity located in or on a substrate; wherein at least one of the source and the drain comprises a first structure comprising: a first region forming a first drift region, the first region being of a second doping polarity opposite the first doping polarity; a second region of the second doping polarity in or on the first region, the second region being a well region and having a doping concentration which is higher than the doping concentration of the first region; and a third region of the second doping polarity in or on the second region. Due to the presence of the second region the transistor may have a lower ON resistance when compared with a similar transistor which does not have the second region. The breakdown voltage may be influenced only to a small extent.

First claim

What is claimed is:

1. A Metal Oxide Semiconductor (MOS) power transistor comprising:
a source;
a gate; and
a drain,
the source, gate and drain being located in or on a well structure of a first doping polarity located in or on a substrate;
wherein each of the source and the drain is provided with a first structure comprising:
a first region forming a first drift region, the first region being of a second doping polarity opposite the first doping polarity;
a second region of the second doping polarity in the first region, the second region being a well region and having a doping concentration which is higher than the doping concentration of the first region;
a third region of the second doping polarity in or on the second region, wherein the third region does not contact the first region and wherein the doping concentration of the first region is such that the first region is substantially fully depleted, and breakdown occurs at a junction between the first region and the well structure, the junction being substantially parallel to the surface of the device; and
a pair of isolators disposed at least partially in the first drift region, wherein the third region is surrounded by the second region and the pair of isolators so that during operation of the transistor current flowing between the source and the drain must pass through the second region.

2. A transistor according to claim 1 , wherein the doping concentration of the second region is between half an order and two orders higher than the doping concentration of the first region.

3. A transistor according to claim 1 , wherein a source or drain terminal is respectively connected to the third region.

4. A transistor according to claim 1 , wherein the thickness of the second region is less than the thickness of the first region.

5. A transistor according to claim 1 , wherein the doping concentrations and thicknesses of the first, second and third regions are such that the ON resistance of the resistor is reduced when compared with a transistor of similar construction but without the second region.

6. A transistor according to claim 1 , wherein the doping concentrations and thicknesses of the first, second and third regions are such that the breakdown voltage is not significantly reduced when compared with a transistor of similar construction but without the second region.

7. A transistor according to claim 1 , wherein the doping concentration of the first region is between 1 E15 and 1 E17.

8. A transistor according to claim 1 , wherein the doping concentration of the second region is between 1 E16 and 1 E18.

9. A transistor according to claim 1 , wherein the thickness of the first region is between 1 μm and 3 μm.

10. A transistor according to claim 1 , wherein the thickness of the second region is between 0.2 μm and 1 μm.

11. A transistor according to claim 1 , wherein: the doping concentration of the third region is between about 2 and 4 orders higher than the doping concentration of the second region.

12. The transistor of claim 1 , wherein the power transistor is configured to operate with a drain to source voltage of 15 volts and above.

13. The transistor of claim 1 , wherein the transistor is a symmetrical transistor.

14. A transistor according to claim 1 , wherein the transistor comprises insulating end caps, each insulating end cap being laterally adjacent the gate.

15. The transistor according to claim 1 and comprising a field plate laterally extending from the gate.

16. The transistor according to claim 15 , wherein the field plate at least partially covers the first set of isolators.

17. The transistor according to claim 15 , wherein the field plate is arranged to reduce field crowding at the drain.

18. A high voltage N-channel lateral diffused Metal Oxide Semiconductor (LDMOS) transistor comprising:
a P-doped substrate;
a P-well disposed in said substrate;
a first N − doped region disposed in the P-well, the first N − doped region forming a first drift region;
a first N-well with a concentration one order higher than that of the first N − doped region, the first N-well being disposed in the first N − doped region;
a first N + doped region disposed in said first N-well;
a source terminal coupled to said first N + doped region;
a second N − doped region disposed in the P-well, the second N − doped region forming a second drift region;
a second N-well with a concentration one order higher than that of the second N − doped region, the second N-well being disposed in the second N − doped region;
a second N + doped region disposed in said second N-well;
a drain terminal coupled to said second N + doped region;
two P + doped regions disposed in the P-well;
a body terminal coupled to said P + doped regions;
a channel region in the body region between the edges of the source and drain drift regions;
a dielectric layer grown over the channel region and a portion of the first and second drift regions defining a drift overlay channel active of both the source and the drain;
a first pair of isolators disposed in said first and second drift regions respectively, said first pair of isolators comprising a dielectric material that is in contact with said dielectric layer;
a gate disposed over said dielectric layer and a portion of said first pair of isolators;
a second pair of isolators disposed at least partially in said first and second drift regions respectively, said second pair of isolators comprising a dielectric material and isolating said first N + doped region and said second N + doped region from said P + doped regions respectively, wherein the first N+ doped region does not contact the first N− doped region and the second N+ doped region does not contact the second N− doped region, wherein the doping concentration of the first N − doped region is such that the first N − doped region is substantially fully depleted, and breakdown occurs at a junction between the first N − doped region and the P-well, the junction being substantially parallel to the surface of the device, and wherein the doping concentration of the second N − doped region is such that the second N − doped region is substantially fully depleted, and breakdown occurs at a junction between the second N − doped region and the P-well, the junction being substantially parallel to the surface of the device; and
wherein the first N+ doped region is surrounded by the first N-well and the isolators disposed at least partially in the first drift region, and wherein the second N+ doped region is surrounded by the second N-well and the isolators disposed at least partially in the second drift region, so that during operation of the transistor current flowing between the source terminal and the drain terminal must pass through the first and second N-wells.

19. The transistor of claim 18 , wherein the first N doped region is a LDD (lightly doped drain) region and wherein the channel region is between the edges of the source LDD and drain drift region, and wherein the dielectric layer is grown over the P-well and a portion of the N-drift and N-LDD regions.

20. The transistor of claim 18 , wherein the transistor has at least one feature selected from the following list:
(a) said gate comprises N + doped polysilicon,
(b) said dielectric material is silicon dioxide,
(c) said isolators are formed with a STI process,
(d) the MOSFET is fabricated using a process technology of 0.18 micrometer, and
(e) the N-wells are formed using a standard process.

Assignees

• Kho Elizabeth Ching Tee
• Liu Zheng Chao
• Pal Deb Kumar
• Tiong Michael Mee Gouh
• Liu Jian
• Kee Kia Yaw
• X-Fab Semiconductor Foundries Ag

Inventors

• Hu Yong Hai
• Kho Elizabeth Ching Tee
• Liu Zheng Chao
• Pal Deb Kumar
• Tiong Michael Mee Gouh
• Liu Jian
• Kee Kia Yaw
• Lau William

Classifications

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H01L29/0653

  Electricity · mapped topic

• H01L29/7835

  Electricity · mapped topic

• H01L29/42368

  Electricity · mapped topic

• H01L29/7834 Primary

  Electricity · mapped topic