Multi-die ultrafine pitch patch architecture of interconnect bridge over glass layer and method of making

Patent metadata

Field	Value
Publication number	US-12142568-B2
Application number	US-202318139275-A
Country	US
Kind code	B2
Filing date	Apr 25, 2023
Priority date	Jul 29, 2019
Publication date	Nov 12, 2024
Grant date	Nov 12, 2024

Abstract

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).

First claim

What is claimed is:

1. A semiconductor package, comprising:
an interconnect bridge over a glass layer, wherein the interconnect bridge is coupled to the glass layer by an adhesive layer;
a substrate over the interconnect bridge and the glass layer, wherein the substrate is conductively coupled to the glass layer by at least two through mold vias (TMVs), wherein the substrate comprises at least two redistribution layers; and
at least two dies over the substrate, wherein the substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and to the glass layer.

2. The semiconductor package of claim 1 , further comprising a mold layer between the glass layer and the substrate, wherein the interconnect bridge is at least partially in the mold layer.

3. The semiconductor package of claim 1 , wherein the glass layer includes a plurality of through glass vias (TGVs).

4. The semiconductor package of claim 3 , wherein the glass layer includes a plurality of first conductive pads and a plurality of second conductive pads, and wherein the interconnect bridge includes a plurality of third conductive pads.

5. The semiconductor package of claim 4 , wherein the plurality of first conductive pads are on a bottom surface of the glass layer, wherein the plurality of second conductive pads are on a top surface of the glass layer, wherein the plurality of third conductive pads are on a top surface of the interconnect bridge, wherein the adhesive layer is directly coupled to the top surface of the glass layer, wherein the plurality of TGVs extend vertically between the bottom surface and the top surface of the glass layer, and wherein the plurality of TGVs conductively couple the plurality of first conductive pads to the plurality of second conductive pads.

6. The semiconductor package of claim 5 , wherein the substrate is a first substrate, wherein the mold layer is a first mold layer, the semiconductor package further comprising:
a second substrate under the glass layer, wherein the plurality of first conductive pads of the glass layer are conductively coupled to the second substrate with a plurality of first solder balls;
a first underfill material over the second substrate, wherein the first underfill material is between the bottom surface of the glass layer and a top surface of the second substrate, wherein the first underfill material surrounds the plurality of first solder balls;
a plurality of fourth conductive pads on the first substrate, wherein the plurality of fourth conductive pads are conductively coupled to the plurality of dies with a plurality of second solder balls;
a second underfill material over the first substrate, wherein the second underfill material is between a bottom surface of the plurality of dies and a top surface of the first substrate, wherein the second underfill material surrounds the plurality of second solder balls; and
a second mold layer over the plurality of dies, the second underfill material, and the first substrate.

7. The semiconductor package of claim 6 , wherein the first mold layer has a top surface that is substantially coplanar to top surfaces of the plurality of TMVs and to top surfaces of the plurality of third conductive pads, and wherein the second mold layer has a top surface that is substantially coplanar to top surfaces of the plurality of dies.

8. The semiconductor package of claim 6 , wherein the plurality of TMVs have a thickness that is substantially equal to a thickness of the plurality of third conductive pads, to a thickness of the interconnect bridge, and to a thickness of the adhesive layer, wherein a first portion of the plurality of fourth conductive pads are positioned directly over the interconnect bridge, wherein a second portion of the plurality of fourth conductive pads are not positioned directly over the interconnect bridge, and wherein the first portion of the plurality of fourth conductive pads has a width that is less than a width of the second portion of the plurality of fourth conductive pads.

9. The semiconductor package of claim 1 , wherein the interconnect bridge includes a plurality of through silicon vias (TSVs).

10. A device comprising:
a glass layer, the glass layer having first and second through glass vias (TGVs);
a mold layer over the glass layer, the mold layer having first and second through mold vias (TMVs);
an interconnect bridge in or on the mold layer, the interconnect bride over the glass layer;
a substrate over the interconnect bridge and the mold layer, the substrate comprising first and second redistribution layers, the substrate comprising first and second conductive interconnects, the first and second conductive interconnects extending through the first and second redistribution layers;
first and second dies over the substrate;
wherein the first die is conductively coupled to the first TGV by the first conductive interconnect and the first TMV; and
wherein the second die is conductively coupled to the second TGV by the second conductive interconnect and the second TMV.

11. The device of claim 10 , wherein the interconnect bridge comprises first and second through silicon vias (TSVs).

12. The device of claim 10 , wherein a distance between the first conductive interconnect and the second conductive interconnect comprises less than six microns.

13. The device of claim 10 , wherein the substrate further comprises a conductive trace between the first conductive interconnect and the second conductive interconnect, wherein a distance between the conductive trace and first conductive interconnect is less than two microns.

14. The device of claim 10 , wherein the mold layer comprises a first mold layer, the device further comprising:
a second mold layer between the substrate and the first and second dies.

15. The device of claim 10 , wherein the substrate comprises a first substrate, the device further comprising:
a second substrate, wherein the second substrate is under the glass layer.

16. A device comprising:
a glass layer having a lower surface and an upper surface opposite the lower surface, the lower surface having a first set of conductive pads, the upper surface having a second set of conductive pads, the glass layer having at least two through glass vias (TGVs) therein, the TGVs conductively coupling the first set of conductive pads to the second set of conductive pads;
a mold layer over at least the upper surface of the glass layer, the mold layer having an upper surface, the mold layer having at least two through mold vias (TMVs) therein;
a bridge die in the mold layer; and
a substrate over the upper surface of the mold layer and over the bridge die, the substrate comprising at least two redistribution layers, the substrate having at least to conductive interconnects, wherein the TMVs are conductively coupled to the conductive interconnects.

17. The device of claim 16 , further comprising first and second dies over the substrate and conductively coupled to the TMVs.

18. The device of claim 17 , wherein the at least two TMVs comprise first and second TMVs, wherein the bridge die is between the first TMV and the second TMV, wherein the first die is over the bridge die and over the first TMV, and wherein the second die is over the bridge die and over the second TMV.

19. The device of claim 17 , wherein the at least two TMVs comprise first and second TMVs, wherein the at least two TGVs comprise first and second TGVs, wherein the first TMV conductively couples the first die to the first TGV, and where

Assignees

• Intel Corp

Inventors

• Ganesan Sanka
• Mccarthy Kevin
• Tribolet Leigh M
• Mallik Debendra
• Mahajan Ravindranath V
• Sankman Robert L

Classifications

• H10W70/618

  the bridge chips being embedded in the package substrates, interposers or redistribution layers · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/874

  On different surfaces · CPC title