Semiconductor device having a thermal contact and method of making

Patent metadata

Field	Value
Publication number	US-12142542-B2
Application number	US-202318447927-A
Country	US
Kind code	B2
Filing date	Aug 10, 2023
Priority date	Nov 20, 2020
Publication date	Nov 12, 2024
Grant date	Nov 12, 2024

Abstract

An integrated circuit includes a substrate and a semiconductor material layer over the substrate. The integrated circuit includes a first source structure in the semiconductor material layer. The first source structure includes a first doped well. The integrated circuit includes a drain structure in the semiconductor material layer. The drain structure includes a second doped well. The integrated circuit includes a second source structure in the semiconductor material layer. The second source structure includes a third doped well. The drain structure is between the first source structure and the second source structure. The integrated circuit includes a first deep trench isolation (DTI) extending through the first doped well; and a first thermal contact extending through the first DTI. The thermal contact is in direct contact with the substrate. The first DTI is between the thermal contact and the first doped well.

First claim

What is claimed is:

1. An integrated circuit comprising:
a substrate;
a semiconductor material layer over the substrate;
a first source structure in the semiconductor material layer, wherein the first source structure comprises a first doped well having a first dopant type;
a drain structure in the semiconductor material layer, wherein the drain structure comprises a second doped well having the first dopant type;
a second source structure in the semiconductor material layer, wherein the second source structure comprises a third doped well having the first dopant type, wherein the drain structure is between the first source structure and the second source structure;
a first deep trench isolation (DTI) extending through the first doped well; and
a first thermal contact extending through the first DTI, wherein the thermal contact is in direct contact with the substrate; and the first DTI is between the thermal contact and the first doped well.

2. The integrated circuit of claim 1 , further comprising an interconnect structure over the semiconductor material layer, wherein the interconnect structure comprises:
a first conductive via electrically connected to the first doped well; and
a second conductive via electrically connected to the first doped well.

3. The integrated circuit of claim 2 , wherein the first thermal contact is between the first conductive via and the second conductive via.

4. The integrated circuit of claim 2 , wherein the first thermal contact is electrically isolated from the interconnect structure.

5. The integrated circuit of claim 1 , wherein the first thermal contact extends above a top-most surface of the semiconductor material layer.

6. The integrated circuit of claim 1 , further comprising a second DTI extending through the second doped well.

7. The integrated circuit of claim 6 , further comprising a second thermal contact extending through the second DTI, wherein the second DTI is between the second thermal contact and the second doped well.

8. The integrated circuit of claim 7 , wherein the second thermal contact directly contacts the substrate.

9. The integrated circuit of claim 7 , further comprising a shallow trench isolation (STI) structure over the second doped well.

10. The integrated circuit of claim 9 , wherein the second DTI extends through the STI.

11. An integrated circuit comprising:
a substrate;
a semiconductor material layer over the substrate;
a first source structure in the semiconductor material layer, wherein the first source structure comprises a first doped well having a first dopant type;
a drain structure in the semiconductor material layer, wherein the drain structure comprises a second doped well having the first dopant type;
an interconnect structure over the semiconductor material layer;
a first deep trench isolation (DTI) extending through the first doped well; and
a first thermal contact extending through the first DTI, wherein the thermal contact is in direct contact with the substrate; and the first DTI is electrically isolated from the interconnect structure.

12. The integrated circuit of claim 11 , further comprising a second source structure in the semiconductor material layer, wherein the second source structure comprises a third doped well having the first dopant type, wherein the drain structure is between the first source structure and the second source structure.

13. The integrated circuit of claim 12 , further comprising a second DTI extending through the third doped well.

14. The integrated circuit of claim 13 , further comprising a second thermal contact extending through the second DTI.

15. The integrated circuit of claim 11 , further comprising an oxide layer between the substrate and the semiconductor material layer.

16. The integrated circuit of claim 11 , wherein the first thermal contact lands on a top-most surface of the substrate.

17. The integrated circuit of claim 11 , further comprising a shallow trench isolation (STI) over the second doped well.

18. The integrated circuit of claim 17 , further comprising a channel region between the first source structure and the drain structure, wherein the STI directly contacts the channel region.

19. The integrated circuit of claim 11 , wherein a thickness of the first doped well is greater than a thickness of the second doped well in a direction perpendicular to a top surface of the substrate.

20. An integrated circuit comprising:
a substrate;
a semiconductor material layer over the substrate;
a transistor comprising:
a gate structure over the semiconductor material layer;
a first source structure in the semiconductor material layer, wherein the first source structure comprises a first doped well having a first dopant type;
a drain structure in the semiconductor material layer, wherein the drain structure comprises a second doped well having the first dopant type;

a first deep trench isolation (DTI) extending through the first doped well; and
a first thermal contact extending through the first DTI, wherein the thermal contact is in direct contact with the substrate; and the first DTI is between the thermal contact and the first doped well.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Tsmc China Company Ltd

Inventors

• Wu Jian
• Han Feng
• Zhang Shuai

Classifications

• H10W70/023

  Connecting or disconnecting interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/02

  of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W40/228 Primary

  the projecting parts being wire-shaped or pin-shaped · CPC title

• H10W40/22

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title

• H10W40/10 Primary

  Arrangements for heating · CPC title