Ferroelectric memory device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12137572-B2
Application number	US-202117385576-A
Country	US
Kind code	B2
Filing date	Jul 26, 2021
Priority date	Feb 26, 2021
Publication date	Nov 5, 2024
Grant date	Nov 5, 2024

Abstract

Ferroelectric stacks are disclosed herein that can improve retention performance of ferroelectric memory devices. An exemplary ferroelectric stack has a ferroelectric switching layer (FSL) stack disposed between a first electrode and a second electrode. The ferroelectric stack includes a barrier layer disposed between a first FSL and a second FSL, where a first crystalline condition of the barrier layer is different than a second crystalline condition of the first FSL and/or the second FSL. In some embodiments, the first crystalline condition is an amorphous phase, and the second crystalline condition is an orthorhombic phase. In some embodiments, the first FSL and/or the second FSL include a first metal oxide, and the barrier layer includes a second metal oxide. The ferroelectric stack can be a ferroelectric capacitor, a portion of a transistor, and/or connected to a transistor in a ferroelectric memory device to provide data storage in a non-volatile manner.

First claim

What is claimed is:

1. A memory device comprising:
a ferroelectric stack having:
a first electrode and a second electrode;
a first ferroelectric layer and a second ferroelectric layer disposed between the first electrode and the second electrode, wherein the first ferroelectric layer and the second ferroelectric layer include a first dielectric material;
a dielectric layer disposed between the first ferroelectric layer and the second ferroelectric layer, wherein the dielectric layer includes a second dielectric material that is different than the first dielectric material; and
wherein the first dielectric material has a crystalline structure having orthorhombic crystalline phase (O-phase) portions and monoclinic crystalline phase (M-phase) portions, wherein a volume of the M-phase portions in the first dielectric material is less than about 10%.

2. The memory device of claim 1 , wherein the second dielectric material has a non-crystalline structure.

3. The memory device of claim 1 , wherein a grain size of the M-phase portions in the first dielectric material is less than about 3 nm.

4. The memory device of claim 1 , wherein the first dielectric material is a first metal oxide material and the second dielectric material is a second metal oxide material.

5. The memory device of claim 1 , wherein the ferroelectric stack has slanted sidewalls, such that the ferroelectric stack has a tapered width.

6. The memory device of claim 1 , wherein the ferroelectric stack has vertical sidewalls, such that the ferroelectric stack has a uniform width.

7. The memory device of claim 1 , wherein the ferroelectric stack has stepped sidewalls, such that the ferroelectric stack has a varying width.

8. The memory device of claim 1 , wherein a first energy bandgap of the dielectric layer is greater than a second energy bandgap of the first ferroelectric layer and a third energy band gap of the second ferroelectric layer.

9. The memory device of claim 8 , wherein the second energy bandgap of the first ferroelectric layer and the third energy band gap of the second ferroelectric layer are the same.

10. The memory device of claim 1 , wherein the first ferroelectric layer has a first thickness, the second ferroelectric layer has a second thickness, and the dielectric layer has a third thickness, wherein the third thickness is less than the first thickness and the third thickness is less than the second thickness.

11. A device comprising:
a transistor disposed over a substrate;
a ferroelectric memory stack disposed over the substrate, wherein the ferroelectric memory stack includes:
a first electrode and a second electrode, and
a ferroelectric switching layer (FSL) stack disposed between the first electrode and the second electrode, wherein the FSL stack includes a first FSL, a second FSL, and a barrier layer disposed between the first FSL and the second FSL, wherein a first crystalline condition of the barrier layer is different than a second crystalline condition of the first FSL and the second FSL, the first crystalline condition is an amorphous phase, the second crystalline condition is an orthorhombic phase and a monoclinic phase, and a grain size of monoclinic phase portions of the first FSL and the second FSL is less than about 3 nm; and

an interconnect structure disposed over the substrate, wherein the interconnect structure is electrically connected to the transistor and the ferroelectric memory stack.

12. The device of claim 11 , wherein the ferroelectric memory stack is electrically connected to a source/drain region of the transistor by the interconnect structure.

13. The device of claim 12 , wherein the interconnect structure includes:
a first metallization layer forming a first level of the interconnect structure; and
a second metallization layer forming a second level of the interconnect structure, wherein the second level is over the first level and the ferroelectric memory stack is disposed in the interconnect structure between and electrically connected to the first metallization layer and the second metallization layer.

14. The device of claim 11 , wherein the transistor has a metal gate that includes a gate electrode disposed over a gate dielectric, and further wherein the ferroelectric memory stack is electrically connected to the gate electrode.

15. The device of claim 11 , wherein the transistor has a metal gate that includes the ferroelectric memory stack disposed directly on a gate dielectric.

16. The device of claim 11 , wherein the first FSL and the second FSL include hafnium and oxygen and the barrier layer includes aluminum and oxygen.

17. The device of claim 11 , wherein a first energy band gap of the barrier layer is different than a second energy band gap of the first FSL and the second FSL.

18. A method for forming a ferroelectric memory stack, the method comprising:
forming a first electrode layer over a substrate;
forming a first ferroelectric dielectric layer over the first electrode layer, wherein the first ferroelectric dielectric layer has a first crystalline condition, wherein the forming the first ferroelectric dielectric layer includes tuning a first deposition process to suppress growth of non-ferroelectric crystal phases;
forming a dielectric layer over the first ferroelectric dielectric layer, wherein the dielectric layer has a second crystalline condition and the second crystalline condition is different than the first crystalline condition;
forming a second ferroelectric dielectric layer over the dielectric layer, wherein the second ferroelectric dielectric layer has a third crystalline condition and the second crystalline condition is different than the third crystalline condition, wherein the forming the second ferroelectric dielectric layer includes tuning a second deposition process to suppress growth of non-ferroelectric crystal phases; and
forming a second electrode layer over the second ferroelectric dielectric layer.

19. The method of claim 18 , wherein: the forming the first ferroelectric dielectric layer includes tuning the first deposition process to suppress phase transitions of a first ferroelectric dielectric material from an orthorhombic crystalline phase to a monoclinic crystalline phase; the forming the dielectric layer includes tuning a third deposition process to provide the second crystalline condition having an amorphous structure; and the forming the second ferroelectric dielectric layer includes tuning the second deposition process to suppress phase transitions of a second ferroelectric dielectric material from the orthorhombic crystalline phase to the monoclinic crystalline phase.

20. The method of claim 18 , wherein the dielectric layer has a first energy band gap that is greater than a second energy band gap of the first ferroelectric dielectric layer and a third energy band gap of the second ferroelectric dielectric layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wei Yi Yang
• Lin Tzu-Yu
• Lee Bi-Shen
• Trinh Hai-Dang
• Lin Hsing-Lien
• Kuang Hsun-Chung

Classifications

• H10D30/701

  IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs · CPC title

• H10D1/692 Primary

  Electrodes · CPC title

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title

• H10D1/688

  comprising barrier layers to prevent diffusion of hydrogen or oxygen · CPC title

• H10D1/68

  Capacitors having no potential barriers · CPC title