Analogue-to-digital conversion circuitry
US-9444479-B2 · Sep 13, 2016 · US
US12136930B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12136930-B2 |
| Application number | US-202217876205-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 28, 2022 |
| Priority date | Sep 8, 2021 |
| Publication date | Nov 5, 2024 |
| Grant date | Nov 5, 2024 |
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The present disclosure provides an analog-to-digital converter system comprising a sampler configured to sample an input signal and provide at least two output signals with a predetermined output sample rate, and an analog-to-digital converter for each one of the output signals and configured to convert the respective output signal into a digital signal with a predetermined converter sample rate, wherein the converter sample rate is higher than the output sample rate. Further, the present disclosure provides a respective method.
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What is claimed is: 1. An analog-to-digital converter system comprising: a sampler configured to sample an input signal and provide at least two output signals with a predetermined output sample rate; an analog-to-digital converter for each one of the output signals and configured to convert the respective output signal into a digital signal with a predetermined converter sample rate, wherein the converter sample rate is higher than the output sample rate; and a signal processor configured to receive the digital signals and to determine the highest signal value and the lowest signal value for at least two samples of the digital signals in each sampling period of the sampler, and to determine a sample value for a respective sample for each one of the digital signals based on the determined highest signal value and lowest signal value. 2. The analog-to-digital converter system according to claim 1 , wherein the signal processor is configured to receive the digital signals and to convert the digital signals into rate-modified digital signals with a sample rate that is different than the converter sample rate. 3. The analog-to-digital converter system according to claim 2 , wherein the sample rate of the rate-modified digital signals is equal to the output sample rate. 4. The analog-to-digital converter system according to claim 1 , wherein the signal processor is configured to receive the digital signals and to perform a sample point adjustment of the digital signals. 5. The analog-to-digital converter system according to claim 1 , wherein the signal processor is configured to receive the digital signals and to down convert the digital signals. 6. The analog-to-digital converter system according to claim 1 , wherein the signal processor is configured to receive the digital signals and to filter the digital signals. 7. The analog-to-digital converter system according to claim 1 , wherein the signal processor is configured to receive the digital signals and to at least one of sum at least two samples of each one of the digital signals prior to determining the sample value for the respective rate-modified signal or to integrate each one of the digital signals over a predetermined amount of time prior to determining the sample value for the respective rate-modified signal. 8. The analog-to-digital converter system according to claim 1 , wherein the signal processor is configured to receive the digital signals and to perform at least one of a static non-linearity correction on the digital signals and a dynamic non-linearity correction on the digital signals and a droop correction on the digital signals. 9. The analog-to-digital converter system according to claim 1 , wherein the sampler comprises a switch that consecutively provides the input signal to a plurality of sample circuits. 10. A method for converting analog signals into digital signals, the method comprising: sampling an input signal and providing at least two output signals with a predetermined output sample rate based on the sampled input signal; converting each one of the output signals into a digital signal with a predetermined converter sample rate, wherein the converter sample rate is higher than the output sample rate; determining the highest signal value and the lowest signal value for at least two samples of the digital signals in each sampling period; and determining a sample value for a respective sample for each one of the digital signals based on the determined highest signal value and lowest signal value. 11. The method according to claim 10 , further comprising: converting the digital signals into rate-modified digital signals with a sample rate that is different than the converter sample rate. 12. The method according to claim 11 , wherein the sample rate of the rate-modified digital signals is equal to the output sample rate. 13. The method according claim 10 , further comprising: performing a sample point adjustment of the digital signals. 14. The method according to claim 10 , further comprising: down converting the digital signals. 15. The method according to claim 10 , further comprising at least of one: summing at least two samples of each one of the digital signals prior to determining the sample value for the respective rate-modified signal, or integrating each one of the digital signals over a predetermined amount of time prior to determining the sample value for the respective rate-modified signal. 16. The method according to claim 10 , further comprising: performing a static non-linearity correction on the digital signals. 17. The method according to claim 10 , further comprising: performing a dynamic non-linearity correction on the digital signals. 18. The method according to claim 10 , further comprising: performing a droop correction on the digital signals.
using time-division multiplexing · CPC title
Details of sampling arrangements or methods · CPC title
Clamping, i.e. adjusting the DC level of the input signal to a predetermined value · CPC title
by filtering · CPC title
Multi-rate systems, i.e. adaptive to different fixed sampling rates · CPC title
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